Samsung S3C2500B Manuals

Manuals and User Guides for Samsung S3C2500B. We have 1 Samsung S3C2500B manual available for free PDF download: User Manual

Samsung S3C2500B User Manual (623 pages)

Brand: Samsung | Category: Computer Hardware | Size: 2.99 MB

Important Notice
3
Table of Contents
4
List of Figures
18
List of Tables
26
Chapter 1 Product Overview

35
- Overview
  35
- Features
  36
- Block Diagram
  39
- Package Diagram
  40
- Pin Assignment
  41
- Signal Description
  47
- Pad Type
  65
- Special Registers
  66
Chapter 2 Programmer's Model

81
- Overview
  81
- Switching State
  81
  - Entering THUMB State
    81
  - Entering ARM State
    81
- Memory Formats
  82
  - Big-Endian Format
    82
  - Little-Endian Format
    82
- Data Types
  83
- Instruction Length
  83
- Operating Modes
  83
- Registers
  84
  - The Relationship between ARM and THUMB State Registers
    87
  - Accessing Hi-Registers in THUMB State
    88
- The Program Status Registers
  88
  - The Condition Code Flags
    89
  - The Control Bits
    89
- Exceptions
  91
  - Action on Entering an Exception
    91
  - Action on Leaving an Exception
    91
  - Exception Entry/Exit Summary
    92
  - Fiq
    92
  - Irq
    93
  - Abort
    93
  - Software Interrupt
    94
  - Undefined Instruction
    94
- Exception Vectors
  94
  - Exception Priorities
    95
  - Not All Exceptions Can Occur at Once
    95
- Interrupt Latencies
  96
- Reset
  96
- Introduction for ARM940T
  97
- ARM940T Block Diagram
  98
- About the ARM940T Programmer's Model
  99
  - Data Abort Model
    100
  - Instruction Set Extension Spaces
    100
- ARM940T CP15 Registers
  101
  - CP15 Register Map Summary
    101
Chapter 3 Instruction Set

113
- Instruction Set Summay
  113
  - Format Summary
    113
  - Instruction Summary
    114
- The Condition Field
  116
- Branch and Exchange (BX)
  117
  - Instruction Cycle Times
    117
  - Assembler Syntax
    117
  - Using R15 as an Operand
    117
- Branch and Branch with Link (B, BL)
  119
  - The Link Bit
    119
  - Instruction Cycle Times
    119
  - Assembler Syntax
    120
- Data Processing
  121
  - CPSR Flags
    123
  - Shifts
    124
  - Immediate Operand Rotates
    128
  - Writing to R15
    128
  - Using R15 as an Operand
    128
  - Teq, Tst, Cmp and CMN Opcodes
    128
  - Instruction Cycle Times
    129
  - Assembler Syntax
    129
- PSR Transfer (MRS, MSR)
  131
  - Operand Restrictions
    131
  - Reserved Bits
    133
  - Instruction Cycle Times
    133
  - Assembler Syntax
    134
- Multiply and Multiply-Accumulate (MUL, MLA)
  135
  - CPSR Flags
    136
  - Instruction Cycle Times
    136
  - Assembler Syntax
    136
- Multiply Long and Multiply-Accumulate Long (Mull,Mlal)
  137
  - Operand Restrictions
    137
  - CPSR Flags
    138
  - Instruction Cycle Times
    138
  - Assembler Syntax
    139
- Single Data Transfer (LDR, STR)
  140
  - Offsets and Auto-Indexing
    141
  - Shifted Register Offset
    141
  - Bytes and Words
    141
  - Use of R15
    143
  - Restriction on the Use of Base Register
    143
  - Data Aborts
    143
  - Instruction Cycle Times
    143
  - Assembler Syntax
    144
- Chapter 3 Instruction Set (Continued)
  144
  - Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH)
    146
    
    Offsets and Auto-Indexing
    147
    
    Half-Word Load and Stores
    148
    
    Signed Byte and Half-Word Loads
    148
    
    Endianness and Byte/Half-Word Selection
    148
    
    Use of R15
    149
    
    Data Aborts
    149
    
    Instruction Cycle Times
    149
    
    Assembler Syntax
    150
  - Block Data Transfer (LDM, STM)
    152
    
    The Register List
    152
    
    Addressing Modes
    153
    
    Address Alignment
    153
    
    Use of the S Bit
    155
    
    Use of R15 as the Base
    155
    
    Inclusion of the Base in the Register List
    156
    
    Data Aborts
    156
    
    Instruction Cycle Times
    156
    
    Assembler Syntax
    157
  - Single Data Swap (SWP)
    159
    
    Bytes and Words
    159
    
    Use of R15
    159
    
    Data Aborts
    160
    
    Instruction Cycle Times
    160
    
    Assembler Syntax
    160
  - Software Interrupt (SWI)
    161
    
    Return from the Supervisor
    161
    
    Comment Field
    161
    
    Instruction Cycle Times
    161
    
    Assembler Syntax
    162
  - Coprocessor Data Operations (CDP)
    163
    
    Coprocessor Instructions
    163
    
    The Coprocessor Fields
    163
    
    Instruction Cycle Times
    164
    
    Assembler Syntax
    164
  - Coprocessor Data Transfers (LDC, STC)
    165
    
    The Coprocessor Fields
    165
    
    Addressing Modes
    166
    
    Address Alignment
    166
    
    Use of R15
    166
    
    Data Aborts
    166
    
    Instruction Cycle Times
    166
    
    Assembler Syntax
    167
- Chapter 3 Instruction Set (Continued)
  167
- Coprocessor Register Transfers (MRC, MCR)
  168
  - The Coprocessor Fields
    168
  - Transfers to R15
    169
  - Transfers from R15
    169
  - Instruction Cycle Times
    169
  - Assembler Syntax
    169
- Undefined Instruction
  170
  - Instruction Cycle Times
    170
  - Assembler Syntax
    170
- Instruction Set Examples
  171
- Thumb Instruction Set Format
  176
  - Format Summary
    176
  - Opcode Summary
    177
- Format 1: Move Shifted Register
  179
  - Operation
    179
  - Instruction Cycle Times
    179
- Format 2: Add/Subtract
  180
  - Operation
    180
  - Instruction Cycle Times
    181
- Format 3: Move/Compare/Add/Subtract Immediate
  182
  - Operations
    182
  - Instruction Cycle Times
    182
- Format 4: ALU Operations
  183
  - Operation
    183
  - Instruction Cycle Times
    184
- Format 5: Hi-Register Operations/Branch Exchange
  185
  - Operation
    185
  - Instruction Cycle Times
    186
  - The Bx Instruction
    186
  - Using R15 as an Operand
    187
- Format 6: PC-Relative Load
  188
  - Operation
    188
  - Instruction Cycle Times
    188
- Format 7: Load/Store with Register Offset
  189
  - Operation
    189
  - Instruction Cycle Times
    190
- Format 8: Load/Store Sign-Extended Byte/Half-Word
  191
  - Operation
    191
  - Instruction Cycle Times
    192
- Chapter 3 Instruction Set (Continued)
  192
- Format 9: Load/Store with Immediate Offset
  193
  - Operation
    193
  - Instruction Cycle Times
    194
- Format 10: Load/Store Half-Word
  195
  - Operation
    195
  - Instruction Cycle Times
    195
- Format 11: SP-Relative Load/Store
  196
  - Operation
    196
  - Instruction Cycle Times
    196
- Format 12: Load Addres
  197
  - Operation
    197
  - Instruction Cycle Times
    198
- Format 13: Add Offset to Stack Pointer
  199
  - Operation
    199
  - Instruction Cycle Times
    199
- Format 14: Push/Pop Registers
  200
  - Operation
    200
  - Instruction Cycle Times
    201
- Format 15: Multiple Load/Store
  202
  - Operation
    202
  - Instruction Cycle Times
    202
- Format 16: Conditional Branch
  203
  - Operation
    203
  - Instruction Cycle Times
    204
- Format 17: Software Interrupt
  205
  - Operation
    205
  - Instruction Cycle Times
    205
- Format 18: Unconditional Branch
  206
  - Operation
    206
- Format 19: Long Branch with Link
  207
  - Operation
    207
  - Instruction Cycle Times
    208
- Instruction Set Examples
  209
Chapter 4 System Configuration

213
- Overview
  213
- Features
  213
- Address Map
  214
- Remap of Memory Space
  215
- External Address Translation
  215
- Arbitration Scheme
  216
  - Problem Solvings with Programmable Round-Robin
    219
- Clock Configuration
  221
- External Bus Master
  226
- System Configuration Special Registers
  227
  - System Configuration Register
    228
  - Product Code and Revision Number Register
    230
  - Clock Control Register
    231
  - Peripheral Clock Disable Register
    232
  - Clock Status Register
    233
  - AHB Bus Master Priority Register
    233
  - Core PLL Control Register
    234
  - System Bus PLL Control Register
    235
  - USB PLL Control Register
    236
  - PHY PLL Control Register
    236
Chapter 5 Memory Controller

237
- Overview
  237
- Features
  238
- Memory Map
  239
- Bus Interface Signals
  241
- Endian Modes
  243
- Ext I/O Bank Controller
  249
  - Features
    249
  - External Device Connection
    250
  - Ext. I/O Bank Controller Special Register
    257
  - Timing Diagram
    265
- SDRAM Controller
  274
  - Features
    274
  - SDRAM Size and Configuration
    275
  - Address Mapping
    278
  - SDRAM Commands
    280
  - External Data Bus Width
    281
  - Merging Write Buffer
    281
  - Self Refresh
    281
  - Basic Operation
    282
  - SDRAM Special Registers
    283
  - SDRAM Controller Timing
    290
Chapter 6 I 2 C Controller

297
- Overview
  297
- Features
  297
- Functional Description
  298
- I 2 C Concepts
  299
  - Basic Operation
    299
  - General Characteristics
    300
  - Bit Transfers
    300
  - Data Validity
    301
  - Start and Stop Conditions
    301
  - Data Trsansfer Operations
    302
- I 2 C Special Registers
  305
  - Control Status Register
    305
  - Shift Buffer Register
    307
  - Prescaler Register
    307
  - Prescaler Counter Register
    308
  - Interrupt Pending Register
    308
Chapter 7 Ethernet Controller

311
- Overview
  311
- Features
  312
- MAC Function Blocks
  313
  - Media Independent Interface (MII)
    313
  - Physical Layer Entity (PHY)
    314
  - Buffered Dma Interface (BDI)
    314
  - The MAC Transmitter Block
    314
  - The MAC Receiver Block
    316
  - Flow Control Block
    317
  - Buffered DMA (BDMA) Overview
    317
- Ethernet Controller Special Registers
  323
  - BDMA Relative Special Register
    325
  - MAC Relative Special Register
    334
  - MAC Frame Format
    347
- Ethernet Operations
  347
  - The MII Station Manager
    355
  - Full-Duplex Pause Operations
    356
  - Error Signalling
    358
  - Timing Parameters for MII Transactions
    360
Chapter 8 HDLC Controller

361
- Overview
  361
- Features
  362
- Function Descriptions
  363
  - HDLC Frame Format
    364
- Protocol Features
  366
  - Invalid Frame
    366
  - Abort
    366
  - Idle and Time Fill
    366
  - FIFO Structure
    367
  - Two-Channel DMA Engine
    367
  - Baud Rate Generator
    367
  - Digital Phase-Locked Loop (DPLL)
    369
  - Clock Usage Method
    369
- HDLC Operational Description
  371
  - HDLC Initialization
    371
  - HDLC Data Encoding/Decoding
    372
  - HDLC Data Setup and Hold Timing with Clock
    373
  - HDLC Transmitter Operation
    374
  - HDLC Receiver Operation
    376
  - Hardware Flow Control
    377
  - Memory Data Structure
    379
  - Data Buffer Descriptor
    380
- Buffer Descriptor
  381
  - Transmit Buffer Descriptor
    381
  - Receive Buffer Descriptor
    382
- HDLC Special Registers
  384
  - HDLC Global Mode Register
    387
  - HDLC Control Register
    390
  - HDLC Status Register
    396
  - HDLC Interrupt Enable Register
    402
  - HDLC Tx Fifo
    404
  - HDLC Rx Fifo
    405
  - HDLC Brg Time Constant Registers
    406
  - HDLC Preamble Constant Register
    407
  - Dma Tx Buffer Descriptor Pointer Register
    409
  - Dma Rx Buffer Descriptor Pointer Register
    410
  - Maximum Frame Length Register
    410
  - Receive Buffer Size Register
    411
  - Synchronization Register
    411
  - Transparent Control Register
    412
  - Tx Buffer Descriptor Count Register
    413
  - Rx Buffer Descriptor Count Register
    413
  - Tx Buffer Descriptor Maximum Count Register
    414
  - Rx Buffer Descriptor Maximum Count Register
    414
Chapter 9 IOM2 & TSA Controller

415
- Overview
  415
- Features
  415
- IOM2 Bus
  416
  - B Channels
    417
  - D Channel
    417
  - Monitor Channels
    417
  - Command and Indicate Channels
    417
  - Intercommunication Channels
    417
  - TIC Bus
    417
  - Channel Operation
    418
- TSA (Time Slot Assigner)
  423
  - Overview
    423
  - TSA Block Diagram
    423
  - HDLC External Pin Multiplexed Signals
    424
  - Operation
    424
- IOM2 Special Registers
  425
  - IOM2CON Register
    426
  - IOM2 Status Register
    428
  - IOM2 Interrupt Enable Register
    430
  - IOM2 TIC Bus Address Register
    432
  - IOM2 IC Channel Transmit Data Register
    433
  - IOM2 C/I0 Channel Transmit Data Register
    434
  - IOM2 C/I1 Channel Transmit Data Register
    435
  - IOM2 C/I1 Channel Receive Data Register
    435
  - IOM2 Monitor Channel Transmit Data Register
    436
  - IOM2 Monitor Channel Receive Data Register
    436
  - TSA a Control Register
    437
  - TSA B Control Register
    438
  - TSA C Control Register
    439
  - IOM2STRB (Strobe Register)
    440
Chapter 10 USB Controller

441
- Overview
  441
- Features
  442
- Function Descriptions
  443
  - USB Bus Topology and Physical Connection
    443
  - Frame Generation
    443
  - Packet Formats
    444
  - Bit Stuffing and NRZI Coding
    445
  - Bulk Transactions
    445
  - Control Transactions
    446
  - Interrupt Transactions
    446
- USB Block Descriptions
  447
  - USB Block Overview
    447
  - SIE (Serial Interface Engine) Block
    447
- USB Special Registers
  449
Chapter 11 DES/3DES

497
- Overview
  497
- Feature
  497
- DES/3DES Special Registers
  499
- DES/3DES Operation
  506
- Performance Calculation Guide
  507
Chapter 12 GDMA Controller

508
- Overview
  508
- Feature
  508
- GDMA Special Registers
  510
  - GDMA Programmable Priority Registers
    511
  - GDMA Control Registers
    516
  - GDMA Source/Destination Address Registers
    519
  - GDMA Transfer Count Registers
    520
  - GDMA Run Enable Registers
    521
  - GDMA Interrupt Pending Register
    522
- GDMA Mode Operation
  523
  - Software Mode
    523
  - External GDMA Request Mode
    523
  - HUART Mode
    523
  - DES Mode
    524
- GDMA Function Description
  524
  - GDMA Transfers
    524
  - Starting/Ending GDMA Transfers
    524
  - Data Transfer Modes
    525
- GDMA Transfer Timing Data
  526
  - Single and One Data Burst Mode
    527
  - Single and Four Data Burst Mode
    528
  - Block and One Data Burst Mode
    529
  - Block and Four Data Burst
    530
Chapter 13 Serial I/O (Console UART)

532
- Overview
  532
- Features
  532
- Console UART Special Registers
  534
  - Console UART Control Registers
    535
  - Console UART Status Registers
    539
  - Console UART Interrupt Enable Register
    542
  - UART Transmit Data Register
    544
  - UART Receive Data Register
    545
  - UART Baud Rate Divisor Register
    546
  - Console UART Baud Rate Examples
    547
  - UART Control Character Register 1 and 2
    548
Chapter 14 Serial I/O (High-Speed UART)

552
- Overview
  552
- Features
  552
- High-Speed UART Special Registers
  554
- High-Speed UART Operation
  575
  - FIFO Operation
    575
  - Hardware Flow Control
    575
  - Software Flow Control
    577
  - Auto Baud Rate Detection
    577
Chapter 15 I/O Ports

582
- Overview
  582
- Features
  582
- I/O Port Special Register
  583
Chapter 16 Interrupt Controller

594
- Overview
  594
- Features
  594
- Interrupt Sources
  595
- Interrupt Controller Special Registers
  596
  - Interrupt Mode Registers
    596
  - Interrupt Mask Registers
    598
  - Interrupt Priority Registers
    601
  - Interrupt Offset Register
    602
  - Interrupt by Priority Register
    605
  - Interrupt Test Register
    605
Chapter 1732 -Bit Timers

606
- Overview
  606
- Interval Mode Operation
  607
- Toggle Mode Operation
  607
- Timer Operation Guidelines
  608
- Timer Special Register
  609
  - Timer Mode Register
    609
  - Timer Data Registers
    611
  - Timer Count Registers
    612
  - Timer Interrupt Clear Registers
    613
  - Watchdog Timer Register
    614
Chapter 18 Electrical Data

616
- Overview
  616
- Absolute Maximum Ratings
  616
- Recommended Operating Conditions
  616
- Electrical Data
  616
- DC Electrical Specifications
  617
- Max Power Consumption
  619
- AC Electrical Characteristics
  620
Chapter 19 Mechanical Data

622
- Overview
  622
- Mechanical Data
  622

Samsung Categories

Cell Phone

Monitor

Microwave Oven LCD TV

Air Conditioner

More Samsung Manuals

Samsung S3C2500B Manuals

Samsung S3C2500B User Manual (623 pages)

Table of Contents

Chapter 1 Product Overview

Chapter 2 Programmer's Model

Chapter 3 Instruction Set

Chapter 4 System Configuration

Chapter 5 Memory Controller

Chapter 6 I 2 C Controller

Chapter 7 Ethernet Controller

Chapter 8 HDLC Controller

Chapter 9 IOM2 & TSA Controller

Chapter 10 USB Controller

Chapter 11 DES/3DES

Chapter 12 GDMA Controller

Chapter 13 Serial I/O (Console UART)

Chapter 14 Serial I/O (High-Speed UART)

Chapter 15 I/O Ports

Chapter 16 Interrupt Controller

Chapter 1732 -Bit Timers

Chapter 18 Electrical Data

Chapter 19 Mechanical Data

Related Products

Samsung Categories