Lauterbach TRACE32-ICD Manuals

Lauterbach TRACE32-ICD Manuals

Manuals and User Guides for Lauterbach TRACE32-ICD. We have 3 Lauterbach TRACE32-ICD manuals available for free PDF download: Manual

Lauterbach TRACE32-ICD Manual

Lauterbach TRACE32-ICD Manual (65 pages)

Family Debugger

Brand: Lauterbach | Category: Computer Hardware | Size: 0.74 MB

Table of Contents

PPC600 Family Debugger
1
Table of Contents
2
Introduction
6
Brief Overview of Documents for New Users
6
Warning
7
Signal Level
7
ESD Protection
7
Target Design Requirement/Recommendations
8
General
8
Quick Start
9
Troubleshooting
11
Problems with Memory Access
12
Faq
12
Configuration
13
System Overview
13
Powerpc 600 Family Specific Implementations
14
Breakpoints
14
Software Breakpoints
14
Software Breakpoint Handling
15
On-Chip Breakpoints
17
Software Breakpoints in Interrupt Handlers
18
Breakpoints in FLASH/ROM
18
Breakpoints on Physical or Virtual Addresses
18
Examples for Breakpoints
19
Software Breakpoints
19
On-Chip Program Address Breakpoints
19
On-Chip Data Address Breakpoints
19
Access Classes
20
Access Classes to Memory and Memory Mapped Resources
20
Access Classes to Other Addressable Core and Peripheral Resources
21
Cache
21
Memory Coherency
21
MESI States
22
Little Endian Operation
23
CPU Specific System Commands
24
System.bdmclock
24
Set JTAG Frequency
24
System.cpu
24
Select the CPU Type
24
System.lock
25
Lock and Tristate the Debug Port
25
System.memaccess
25
Real-Time Memory Access (Non-Intrusive)
25
System.mode
26
Select Operation Mode
26
System.config.state
27
Display Target Configuration
27
System.config
28
Configure Debugger According to Target Topology
28
Daisy-Chain Example
31
Tapstates
32
System.config.chkstpin Control Pin 8 of Debug Connector
32
System.config.core Assign Core to TRACE32 Instance
33
System.config.driverstrength
34
Configure Driver Strength of TCK Pin
34
System.config.qack
34
Control QACK Pin
34
CPU Specific System Commands
35
System.option.base
35
Set Base Address for On-Chip Peripherals
35
System.option.bus32
36
Use 32-Bit Data-Bus Mode
36
System.option.config
36
Select RCW Configuration
36
System.option.dcread
37
Read from Data Cache
37
System.option.dualport
37
Implicitly Use Run-Time Memory Access
37
System.option.freeze Freeze Timebase When Core Halted
38
System.option.holdreset
39
Set Reset Hold Time
39
System.option.hook
39
Compare PC to Hook Address
39
System.option.hrcwoverride
40
Override HRCW on System.up
40
System.option.icflush
40
Invalidate Instruction Cache before Go/Step
40
System.option.icread
41
Read from Instruction Cache
41
System.option.imaskasm
41
Disable Interrupts While Single Stepping
41
System.option.imaskhll
41
Disable Interrupts While HLL Single Stepping
41
System.option.ip
42
Set MSR_IP Value for Breakpoints / System.up
42
System.option.littleend
42
True Little Endian Mode
42
System.option.memprotect
42
Enable Memory Access Safeguard
42
System.option.memspeed
43
Configure Memory Access Timing
43
System.option.mmuspaces
43
Separate Address Spaces by Space Ids
43
System.option.nodebugstop
44
Disable JTAG Stop on Debug Events
44
System.option.notrap
45
Use Alternative Software Breakpoint Instruction
45
System.option.overlay
46
Enable Overlay Support
46
System.option.parity
46
Generate Parity on Memory Access
46
System.option.pintdebug
47
Program Interrupt Debugging
47
System.option.ppclittleend
47
PPC Little Endian Mode
47
System.option.pte
48
Evaluate PTE Table for Address Translation
48
System.option.resetbehavior
48
Set Behavior When Target Reset Detected
48
System.option.resetmode
49
Select Reset Mode for System.up
49
System.option.slowreset
49
Relaxed Reset Timing
49
System.option.stepsoft
50
Use Alternative Method for ASM Single Step
50
System.option.waitreset
51
Set Reset Wait Time
51
System.option.watchdog
52
Leave Software Watchdog Enabled
52
CPU Specific MMU Commands
53
Mmu.dump
53
Page Wise Display of MMU Translation Table
53
Mmu.list
55
Compact Display of MMU Translation Table
55
Mmu.scan
57
Load MMU Table from CPU
57
Mmu.set
58
Write MMU TLB Entries to CPU
58
CPU Specific Benchmarkcounter Commands
59
Bmc.<Counter>.Freeze
59
Freeze Counter in Certain Core States
59
BMC.FREEZE Freeze Counters While Core Halted
60
CPU Specific Tronchip Commands
61
Tronchip.disable
61
Disable Debug Register Control
61
Tronchip.enable
61
Enable Debug Register Control
61
Tronchip.convert
61
Adjust Range Breakpoint in On-Chip Resource
61
Tronchip.varconvert
62
Adjust Complex Breakpoint in On-Chip Resource
62
Tronchip.reset
62
Reset On-Chip Trigger Settings
62
Tronchip.state
62
Display On-Chip Trigger Window
62
Tronchip.tenable
62
Set Filter for the Trace
62
Tronchip.toff
63
Switch the Sampling to the Trace to off
63
Tronchip.ton
63
Switch the Sampling to the Trace to "ON
63
Tronchip.ttrigger
63
Set a Trigger for the Trace
63
Mechanical Description
64
JTAG/COP Connector Ppc603E/700/Mpc8200
64
Technical Data
65

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Lauterbach TRACE32-ICD Manual

Lauterbach TRACE32-ICD Manual (53 pages)

PQIII Debugger

Brand: Lauterbach | Category: Computer Accessories | Size: 0.46 MB

Table of Contents

Table of Contents
1
Introduction

4
- Brief Overview of Documents for New Users
  4
Warning

5
Target Design Requirement/Recommendations

6
- General
  6
Quick Start

7
Troubleshooting

8
- System.up Errors
  8
Faq

9
Configuration

10
- System Overview
  10
Powerpc MPC85XX Specific Implementations

11
- Breakpoints
  11
- Access Classes
  15
  - Access Classes to Memory and Memory Mapped Resources
    15
  - Access Classes to Other Addressable Core and Peripheral Resources
    16
- Memory Classes
  17
- Cache
  18
  - Memory Coherency
    18
  - MESI States
    19
- Debugging Information
  20
  - Setting-Up the Debug Interrupt for MPC85XX
    20
  - Multicore Debugging E500 Cores
    21
    
    SMP Debugging
    21
    
    AMP Debugging
    21
    
    Synchronous Stop of both E500 Cores
    21
- Programming Flash on MPC85XX / Qoriq P10XX/P20XX, PSC93XX
  22
- On-Chip Trace on Mpc85Xx/Qoriq
  22
General System Commands

24
- System.bdmclock
  24
  - Set BDM Clock Frequency
    24
- System.config.state
  24
  - Display Target Configuration
    24
- System.config
  26
  - Configure Multi-Core Debugger
    26
  - Example
    27
- System.config.chkstpin
  28
  - Control Pin 8 of Debug Connector
    28
- System.config.driverstrength
  29
  - Configure Driver Strength of TCK Pin
    29
- System.config.qack
  29
  - Control QACK Pin
    29
- System.cpu
  30
  - Select the CPU Type
    30
- System.cpuaccess
  31
  - Run-Time CPU Access (Intrusive)
    31
- System.lock
  31
  - Lock and Tristate the Debug Port
    31
- System.memaccess
  32
  - Run-Time Memory Access (Non-Intrusive)
    32
- System.mode
  33
  - Select Operation Mode
    33
CPU Specific System Commands

34
CPU Specific MMU Commands

42
- Mmu.dump
  42
- Page Wise Display of MMU Translation Table
  42
  - Mmu.list
    44
  - Compact Display of MMU Translation Table
    44
  - Mmu.scan
    45
  - Load MMU Table from CPU
    45
  - Mmu.set
    46
  - Set a MMU TLB Entry
    46
CPU Specific Tronchip Commands

47
- Tronchip.convert
  47
- Adjust Range Breakpoint in On-Chip Resource
  47
MPC85XX Specific Onchip Trace Settings

51
- Onchip.mode.ifsel
  51
- Select Interface to be Traced
  51
CPU Specific Trbus Commands

52
JTAG Connector

53
- Mechanical Description
  53
  - JTAG Connector MPC85XX (COP)
    53

Lauterbach TRACE32-ICD Manual

Lauterbach TRACE32-ICD Manual (56 pages)

StarCore Debugger and Trace

Brand: Lauterbach | Category: Computer Accessories | Size: 0.5 MB

Table of Contents

Starcore Debugger and Trace
1
Table of Contents
2
Introduction
6
Brief Overview of Documents for New Users
6
Warning
7
Quick Start
8
Troubleshooting
11
System.up Errors
11
Memory Access Errors
12
NEXUS Flow Errors and FIFO Overflow Messages
13
Faq
14
Configuration
15
CPU Specific System Settings and Restrictions
16
System.clock
16
Setup Core Clock
16
System.config.state
16
Display Target Configuration
16
System.config
17
Configure Debugger According to Target Topology
17
Daisy-Chain Example
19
Tapstates
20
System.config.core Assign Core to TRACE32 Instance
21
System.cpu
22
Select the Used CPU
22
System.lock
22
Lock and Tristate the Debug Port
22
System.memaccess
22
Real-Time Memory Access (Non-Intrusive)
22
System.mode
24
Establish the Communication with the Target
24
System.option.base
24
Sets the SUI Base Address
24
System.option.dcflush
25
Data Cache Flush before Step/Run
25
System.option.dtm
25
Enables Data Trace Messages
25
System.option.enreset
25
Allow the Debugger to Drive Nreset/Nsrst
25
System.option.entrst
26
Allow Debugger to Drive TRST
26
System.option.halfrate
26
Enable Nexus DDR Mode
26
System.option.icflush
27
Instruction Cache Flush before Step/Run
27
System.option.imaskasm
27
Disable Interrupts While Single Stepping
27
System.option.imaskhll
27
Disable Interrupts While HLL Single Stepping
27
System.option.ipldi
28
Sets Interrupt Mask Strategy
28
System.option.littleend
28
Switches between Endian Modes
28
System.option.mcko
28
Nexus Output Clock Ratio
28
System.option.mpu
29
MPU Disabled
29
System.option.nexus
29
Nexus Port Width
29
System.option.ocebase
29
Base Address for Once Registers
29
System.option.ocecore
30
Once Selection
30
System.option.ovc
30
Trace Message Overrun Control
30
System.option.ptm
30
Enables Program Trace Messages
30
System.option.sample
31
Adjust NEXUS Sample Point
31
System.option.slowpoll
31
Change Timing of JTAG During Runtime
31
System.option.slowreset
31
Expand Reset Time for Additional Reset Module
31
System.option.vba Set up VBA Value for Analysis
32
System.option.waitreset
33
Halt the Core after Reset
33
System.option.watchdog Enable WATCHDOG
34
System.jtagclock Define JTAG Clock
34
CPU Specific MMU Commands
38
Mmu.dump
38
Page Wise Display of MMU Translation Table
38
Mmu.list
38
Compact Display of MMU Translation Table
38
MMU.SCAN Load MMU Table from CPU
39
Benchmarkcounter
40
Tronchip
41
Tronchip Control of On-Chip Resources
44
Tronchip.convert
45
Automatically Convert Range to Single Address
45
Tronchip.register
45
Shows Custom On-Chip Trigger Registers
45
Tronchip.reset
45
Set On-Chip Trigger to Default State
45
Tronchip.varconvert
45
Tronchip.state Opens Configure Panel
46
On-Chip Trace
47
Onchip.mode
47
Select Mode to Control Trace Buffer and Contents
47
Onchip.vtba Set the Destination Address of the Onchip Trace
48
General Restrictions
49
Floating Point Formats
50
Integer Access Keywords
50
File I/O Support
51
Metrowerks MSLIO Support
51
JTAG Connection
52

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