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Manuals and User Guides for Intel Pentium M Processor Computer. We have
1
Intel Pentium M Processor Computer manual available for free PDF download: Design Manual
Intel Pentium M Processor Design Manual (363 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 17.08 MB
Table of Contents
Table of Contents
3
Introduction
19
Reference Documents
19
Terminology
21
Conventions and Terminology
21
System Overview
24
Intel ® Pentium ® M Processor
24
Architectural Features
25
Packaging/Power
25
Enhanced Intel ® Speedstep ® Technology
25
Intel ® Pentium ® M Processor on the 90 Nm Process with 2-MB L2 Cache
26
Intel ® E7501 Chipset
27
Intel E7501 Memory Controller Hub (MCH)
27
I/O Controller Hub 3 (Intel 82801CA ICH3-S) Features
28
PCI/PCI-X 64-Bit Hub 2 (Intel P64H2) Features
28
Peak Bandwidth Summary
29
System Configurations
29
Configuration Example
30
Component Quadrant Layout
31
Intel ® Pentium ® M Processor Quadrant Layout
32
Intel ® E7501 Chipset MCH Quadrant Layout
33
Intel ® E7501 Chipset MCH Quadrant Layout (Top View)
33
Intel ® ICH3-S Quadrant Layout
34
Intel ® P64H2 Quadrant Layout
35
Intel ® P64H2 Quadrant Layout (Top View)
35
Baseboard Requirements
37
Platform Stack-Up
37
Ten Layer Stack-Up, 50 Ω Board with 5-Mil Traces
37
Processor Thermal Solution Placement and Recommended Keep-Outs
38
Board Requirements
38
Platform Clock Routing Guidelines
39
Platform Clock
39
CK408 Clock Groups
39
Platform System Clock Reference
39
System Clocking Diagram Example
41
HOST_CLK Clock Group
42
HOST_CLK Clock Topology
42
Shunt Source Termination
42
HOST_CLK[1:0]# Routing Guidelines
43
Clock Skew as Measured from Agent to Agent
44
BCLK Length Matching Requirements (Mfcpga)
45
HOST_CLK General Routing Guidelines
45
CK408 Vs. CK408B Requirement
46
Stuffing Options for CK408 and CK408B
46
CLK66 Clock Group
47
Topology for CLK66
47
CLK66 Routing Guidelines
47
CLK66 Skew Requirements
48
Clock Skew Requirements
48
Example of Adding a Single Connector
49
Example of Adding Two Connectors And/Or a Riser
49
CLK33_ICH3-S Clock Group
50
CLK33 Clock Group
50
Topology for CLK33_ICH3-S
50
Topology for CLK33 to PCI Device down
50
CLK33_ICH3-S Routing Guidelines
50
Topology for CLK33 to PCI Slot
51
CLK33 Routing Guidelines for PCI Device down
51
CLK33 Routing Guidelines for PCI Slot
51
CLK14 Clock Group
52
Topology for CLK14
52
CLK14 Routing Guidelines
52
USBCLK Clock Group
53
USBCLK Routing Guidelines
53
Clock Driver Decoupling
54
Decoupling Capacitors Placement and Connectivity
54
Clock Driver Power Delivery
55
System Bus Routing Guidelines
57
Design Recommendations
57
System Bus Signals
57
System Bus Signal Groups
57
Processor System Bus Termination
58
Processor System Bus Topology
58
System Bus Routing Summary
58
Recommended Stack-Up Routing and Spacing Assumptions
59
Trace Space to Trace - Reference Plane Separation Ratio
59
Trace Space to Trace Width Ratio
59
Trace Spacing Vs. Trace-Reference Plane Example
59
Processor RESET# Signal
60
Trace Spacing Vs. Trace Width Example
60
Processor RESET# Signal Routing Topology with no ITP700FLEX Connector
60
Source Synchronous Signals
61
Source Synchronous General Routing Guidelines
61
Processor RESET# Signal Routing Topology with ITP700FLEX Connector
61
Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
61
2X and 4X Signal Groups
61
Source Synchronous - Data
62
Signal Trace Length Match Mapping
62
Source Synchronous - Address
63
Data Signal Routing Guidelines
63
Intel ® Pentium ® M Processor System Bus Address Source Synchronous
63
Signal Trace Length Mismatch Mapping
63
Common Clock Signals
64
Address Signal Routing Guidelines
64
Asynchronous Signals
65
Topologies
65
Internal Layer Routing Guidelines
65
Routing Illustration for Topology 1A
66
Routing Illustration for Topology 1B
66
Layout Recommendations for Topology 1A
66
Routing Illustration for Topology 1C
67
Layout Recommendations for Topology 1B
67
Layout Recommendations for Topology 1C
67
Routing Illustration for Topology 2A
68
Layout Recommendations for Topology 2A
68
Layout Recommendations for Topology 2B
68
Voltage Translation Logic
69
AGTL+ I/O Buffer Compensation
70
Intel Pentium M Processor AGTL+ I/O Buffer Compensation
70
Intel E7501 Chipset AGTL+ I/O Buffer Compensation
70
Voltage Translation Circuit
70
Intel ® Pentium ® M Processor System Bus Strapping
71
Resistor Divider Circuit for the Mch's HXSWNG and HYSWNG
71
ITP Signal Default Strapping When ITP Debug Port Not Used
71
Design Recommendations
72
Memory Interface Routing Guidelines
73
DDR Channel Signal Groups
73
DDR Channel Impedance Requirements
74
Trace Width to Impedance Requirements
74
DIMM Types
75
Trace Width and Spacing for All DDR Signals Except Cmdclk_X[3:0]/Cmdclk_X[3:0]
75
Dual Channel DDR Overview
76
DIMM Connector Styles Supported
76
Dual Channel Source Synchronous Signal Group Routing
78
Example of Proper Single and Dual Rank Mixing
78
Example of Incorrect Single and Dual Rank Mixing
78
DQ/CB to DQS Mapping
78
Dual Channel Source Synchronous Signal Group Routing Guidelines
80
Dual Channel Source Synchronous Topology DIMM Solution
81
Trace Length Matching Requirements for Source Synchronous Routing
81
Dual Channel Command Clock Routing
82
Dual Channel Command Clock Pair Routing Guidelines
82
Dual Channel Source Clocked Signal Group Routing
83
Dual Channel 2-DIMM Command Clock Topology
83
Dual Channel Source Clocked Signal Group Routing Guidelines
83
Dual Channel Chip Select Routing
84
Dual Channel Source Clocked Signal Topology
84
Dual Channel Chip Select Routing Guidelines
84
Dual Channel Clock Enable Routing
85
Dual Channel Chip Select Topology
85
Dual Channel DC Biasing Signals
86
Dual Channel CKE Topology
86
Dual Channel Clock Enable Routing Guidelines
86
Dual Channel Receive Enable Signal (RCVEN#)
87
Dual Channel DDRCOMP
87
Dual Channel Receive Enable Signal Routing Guidelines
87
Receive Enable Routing Guidelines
87
DDRCOMP Routing Guidelines
87
Dual Channel DDRVREF and ODTCOMP
88
Dual Channel DDRCOMP Resistive Compensation
88
DDR VREF Voltage Regulator
88
DDR VREF Voltage Divider
89
Dual Channel Routing DDRVREF and ODTCOMP
89
Dual Channel DDRCVO
90
Dual Channel DDR Signal Termination and Decoupling
90
Dual Channel DDRCVO Routing Guidelines
90
DDRCVO Routing Guidelines
90
2.5 Volt Decoupling Requirements
91
DDR Vterm Plane
91
53 1-DIMM Per Channel Decoupling
92
54 2-Dimms Per Channel Decoupling
93
Single Channel DDR Overview
94
Single Channel 2-DIMM Implementation
94
Single Channel 4-DIMM Implementation
95
Example of Proper Single Channel Rank Mixing
95
Unused Channel Termination
96
Example of Incorrect Single Channel Rank Mixing
96
Channel B Signal Terminations
96
Single Channel Source Synchronous Signal Group Routing
97
Single Channel DQ/CB to DQS Mapping
97
Single Channel Source Synchronous Signal Group Routing Guidelines
98
Single Channel Source Synchronous Topology DIMM Solution
99
Trace Length Matching Requirements for Single Channel Source Synchronous Routing
99
Single Channel Command Clock Routing
100
Single Channel 2-DIMM Command Clock Topology
100
Single Channel Command Clock Pair Routing Guidelines
100
Single Channel Source Clocked Signal Group Routing
101
Single Channel Source Clocked Signal Topology
101
Single Channel Chip Select Routing
102
Single Channel Chip Select Topology
102
Single Channel Clock Enable Routing
103
Single Channel CKE Topology
103
Single Channel DC Biasing Signals
104
Single Channel Receive Enable Signal (RCVEN#)
104
Single Channel DDRCOMP
104
Single Channel Receive Enable Signal Routing Guidelines
104
Single Channel DDRVREF and ODTCOMP
105
Single Channel DDRCOMP Resistive Compensation
105
DDR VREF Voltage Regulator
106
DDR VREF Voltage Divider
106
Single Channel DDRCVO
107
Routing Single Channel DDRVREF and ODTCOMP
107
Single Channel DDR Signal Termination and Decoupling
108
Single Channel DDRCVO Single Channel Routing Guidelines
108
2.5 V Decoupling Requirements
109
DDR Vterm Plane
109
Single Channel 2-DIMM Decoupling
110
Single Channel 4-DIMM Decoupling
111
Hub Interface
113
Signal Naming Convention
113
Signal Naming Convention on both Sides of the Hub Interfaces
113
Hub Interface 2.0 Implementation
114
Hub Interface 2.0 High-Speed Routing Guidelines
114
Hub Interface 2.0 Length Matching
116
Hub Interface 2.0 Generation/Distribution of Reference Voltages
117
Hub Interface 2.0 Routing Guidelines for Device down Solutions
117
Hub Interface 2.0 Routing Guidelines for Hub Interface Connector Solutions
117
Hub Interface 2.0 Resistive Compensation
118
Hub Interface 2.0 with Locally Generated Voltage Divider Circuit
118
Hub Interface 2.0 Decoupling Guidelines
119
Unused Hub Interface 2.0 Interfaces
119
Hub Interface 2.0 RCOMP Circuits
119
Hub Interface 1.5 Implementation
120
Hub Interface 1.5 High-Speed Routing Guidelines
120
80 8-Bit Hub Interface 1.5 Routing
120
Hub Interface 1.5 Generation/Distribution of Reference Voltages
121
Hub Interface 1.5 Locally Generated Reference Divider Circuits
121
Hub Interface 1.5 Resistive Compensation
122
Hub Interface 1.5 Decoupling Guidelines
122
Hub Interface 1.5 RCOMP Circuits
122
Intel ® 82870P2 (Intel P64H2)
123
PCI/PCI-X Design Guidelines
123
General PCI-X Routing Guidelines
124
PCI/PCI-X Routing Requirements (no Hot-Plug Switch)
125
PCI/PCI-X Hot-Plug Switch Routing Requirements
125
Typical PCI/PCI-X Bus Topology
125
Riser Card Topologies
126
Typical Hot-Plug Topology
126
PCI-X Riser Card Topology
127
Device down before PCI-X Riser Card Topology
127
PCI-X Two Devices Down-Routing Requirements
128
Device down after PCI-X Riser Card Topology
128
Device down with Stub before PCI-X Riser Card Topology
128
Clock Configuration
129
Two Devices down Card Topology
129
Hot-Plug Clock Topology
129
Loop Clock Configuration
130
No Hot-Plug Clock Topology
130
Loop Clock Topology
130
IDSEL Implementation
131
Smbus Address
131
IDSEL Sample Implementation Circuit
131
Hot-Plug Implementation
132
Standard Usage Model
132
Hot-Removals
133
Hot-Insertions
133
Hot-Plug Switch Implementation
134
Manually-Operated Retention Latch Sensor
134
Optional Attention Button
135
LED Indicator Outputs
135
Hot Plug Interrupt Routing Requirements
135
Attention Button Implementation
135
Hot-Plug Interrupt Routing Requirements
136
Disabling/Enabling an Intel ® P64H2 Hot-Plug Controller
136
Hot-Plug Strapping Options
136
Hot-Plug Registers' Visibility
136
Single-Slot Parallel Mode
136
Required Additional Logic
136
PCI Clock
137
Debounced Hot-Plug Switch Input
137
Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins
137
Tri-State Buffer or 2:1 Multiplexer for Hpx_Slot[2:0]
137
Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode
138
Tri-State Buffer Circuit Example
138
MUX Circuit Example
138
Smbus Address Considerations
139
Single-Slot Parallel Smbus Circuit
140
Pull-Ups/Pull-Downs in Single-Slot Parallel Mode
140
Reference Schematic for Single-Slot Parallel Mode
140
Dual-Slot Parallel Mode
141
Required Additional Logic
141
Reference Schematic for Single-Slot Parallel Mode
141
Debounced Hot-Plug Switch Input
142
Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins
142
Tri-State Buffer or 2:1 Multiplexer for Hpx_Slot[2:0]
142
Hpx_Sid Output Signal
142
Pull-Ups/Pull-Downs in Dual-Slot Parallel Mode
142
Hot-Plug Multiplexed Signals in Dual-Slot Parallel Mode
142
Smbus Address Considerations
144
Reference Schematic for Dual-Slot Parallel Mode
144
Dual-Slot Parallel Smbus Circuit
144
Three or more Slot Serial Mode
145
Hot-Plug and Non-Hot-Plug Combinations
145
Reference Schematic for Dual-Slot Parallel Mode
145
Required Additional Logic
146
Debounced Hot-Plug Switch Input
146
Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins
146
Hpx_Slot[2:0]
146
Stutter Logic for Implementing Fewer than Six Slots
146
Pull-Ups/Pull-Downs in Three or more Slot Serial Mode
147
Four-Slot Stutter Logic Implementation Example
147
Reference Schematic for Serial Mode
148
Intel ® P64H2 PCI Interface PCIXCAP and M66EN Pins
148
PCIXCAP Pin Requirements
148
M66EN Pin Requirements
149
M66EN Isolation Switch Solution
150
M66EN Diode Solution
151
O Controller Hub
153
Ich3-S)
153
IDE Interface
153
Cabling
153
Cable Detection for Ultra ATA/66 and Ultra ATA/100
153
Combination Host-Side/Device-Side Cable Detection
154
Combination Host-Side/Device-Side IDE Cable Detection
154
IDE Connector Requirements
155
Connection Requirements for IDE Connector
155
SPKR Pin Consideration
156
Pci
156
Example Speaker Circuit
156
Usb
157
General Routing and Placement
157
PCI Bus Layout Example
157
USB Routing Parameters
158
EMI Considerations
158
USB Power Line Layout Topologies
158
Intel ® ICH3-S Smbus/Smlink Interface
159
Suggested USB Downstream Power Connection
159
Smbus Design Considerations
160
Intel ® ICH3-S Smbus / Smlink Interface
160
Unified VCC_CORE Architecture
161
High Power/Low Power Mixed Architecture
161
Unified VCC3_3 Architecture
161
High Power/Low Power Mixed VCC_SUSPEND/ VCC_CORE Architecture
161
Calculating the Physical Segment Pull-Up Resistor
162
Real Time Clock (RTC)
163
RTCX1 and SUSCLK Relationship
163
RTC Connection When Not Using Internal RTC
163
RTC External Circuit
164
RTC External RTCRST# Circuit
164
Example of RTC External Circuitry
164
External Capacitors
165
Example with Load Capacitance
165
RTC Layout Considerations
166
RTC External Battery Connection
166
VBIAS DC Voltage and Noise Measurements
166
Susclk
167
RTC-Well Input Strap Requirements
167
Internal LAN Layout Guidelines
168
Platform LAN Connect
168
LCI (LAN Connect Interface) Guidelines
169
Bus Topology
169
LCI Routing Parameters
169
Point-To-Point Interconnect Guideline
169
General LAN Routing Guidelines and Considerations
170
General Trace Routing Considerations
170
LAN_CLK Routing Example
170
Trace Geometry and Length
171
Signal Isolation
171
Routing a 90-Degree Bend
171
Power and Ground Connections
172
General Power and Ground Plane Consideration
172
Ground Plane Separation
172
Board Design
173
Common Physical Layout Issues
173
Intel ® 82562Et/Intel ® 82562EM Guidelines
175
Intel ® 82562Et/Intel ® 82562EM Component Placement Guidelines
175
Crystals and Oscillators
175
Intel ® 82562Et/Intel ® 82562EM Termination Resistors
176
Critical Dimensions
176
Intel ® 82562Et/Intel ® 82562EM Termination
176
Critical Dimensions for Component Placement
176
Distance from Magnetics Module to RJ45 (Distance A)
177
Distance from Intel® 82562ET to Magnetics Module (Distance B)
177
Terminating Unused Connections
177
Termination Plane Capacitance
178
Termination Plane
178
Debug Port and Logic Analyzer Interface
179
ITP Support
179
Overview
179
Implementation
179
Recommended Onboard ITP700FLEX Implementation
180
ITP Signal Routing Guidelines
180
TDI, TMS and TRST# Routing Requirements
180
ITP700FLEX Debug Port Signals
180
TCK and TDO Routing Requirements
181
Bpmx# Routing Requirements
181
RESET# Routing Guidelines
182
BCLK Routing Requirements
182
ITPFLEX Routing Requirement Summary
182
Intel ® Pentium ® M Processor Logic Analyzer Support
184
Overview
184
Implementation
184
Logic Analyzer Interface (LAI)
184
Mechanical Considerations
185
Electrical Considerations
185
Platform Power Delivery Guidelines
187
Processor Voltage Regulator Power Delivery Architectural Block Diagram
188
Customer Reference Board Power Delivery
188
Processor Voltage Regulator Block Diagram
188
Power Delivery Example
189
Processor Core Voltage (VCC_CORE)
190
System Bus Voltage (VCCP 1.05 V)
190
190
190
191
191
Vsb
191
Power Summary
191
Processor Power Delivery Design Guidelines
192
Processor PLL Power Delivery
192
Voltage Identification for Intel ® Pentium ® M Processor
192
Vcc_Core
194
Power Sequencing
194
VCCP Output Requirements
194
Power on Sequencing Timing Diagram
194
Thermal Power Dissipation
195
VCCP Block Diagram
195
Voltage Regulator Topology
196
Voltage Regulator Design Recommendations
197
High Current Path, Top MOSFET Turned on
197
Voltage Regulator Multi-Phase Topology Example
197
Buck Voltage Regulator Example
197
High Current Paths During Abrupt Load Current Changes
198
High Current Paths During Switching Dead Time
198
High Current Path with Top MOSFET Turned on
198
High Current Path During Abrupt Load Current Changes
198
High Current Path with Bottom MOSFET(S) Turned on
199
General Layout Recommendations
199
High Current Path with Top and Bottom Mosfets Turned off (Dead Time)
199
Processor Decoupling Recommendations
201
Transient Response
201
High/MID Frequency and Bulk Decoupling
201
Processor Core Voltage Plane and Decoupling
201
Processor Side Bus Voltage Plane Decoupling
202
GTLREF Layout and Routing Recommendations
202
MCH Power Delivery Guidelines
203
DDR_VTT (1.25 V) Decoupling
203
CPU_VCC (1.05 V Power Plane)
203
Intel ® Pentium ® M Processor GTLREF0 Voltage Divider Network
203
DDR (2.5 V Power Plane)
204
MCH Decoupling (Backside View)
204
Hub Interface (1.2 V Power Plane)
205
Intel ® E7501 Chipset Filter Specifications (1.2 V Power Plane)
205
Filter Topology for VCCA1_2 (DDR Interface)
205
MCH Power Sequencing Requirement
206
Filter Topology for VCCAHI1_2 (Hub Interface)
206
Filter Topology for VCCACPU1_2 (E7501 System Bus)
206
Power Sequencing Requirement for MCH
206
Intel ® ICH3-S Power Delivery Guidelines
207
V/3.3 V Power Sequencing
207
Sample 2.5 V Output Enable Control Logic
207
Intel
207
Cc_3.3
207
Example 1.8 V/3.3 V Power Sequencing Circuit
208
V5REF Sequencing
209
Another Example 1.8 V/3.3 V Power Sequencing Circuit
209
Example 3.3 V/V5REF Sequencing Circuitry
209
Intel ® ICH3-S Power Rails
210
Intel ® ICH3-S Decoupling Recommendations
210
Intel ® P64H2 Power Requirements
212
Intel ® P64H2 Current Requirements
212
Intel ® P64H2 Decoupling Requirements
212
PCIRST# Implementation
213
Intel ® P64H2 Power Sequencing Requirement
213
High-Speed Design Concerns
215
Return Path
215
Decoupling Theory
215
Bulk Decoupling
216
High-Frequency Decoupling
216
Proper Decoupling Capacitor Placement with Respect to Vias
216
Serpentine Routing
217
EMI Design Considerations
218
Brief EMI Theory
218
EMI Regulations and Certifications
218
EMI Design Considerations
219
Spread Spectrum Clocking (SSC)
219
Differential Clocking
220
PCI Bus Clock Control
221
EMI Test Capabilities
221
Length Tuning
222
Signal to Strobe Flight Time Relationships
222
Flight Time Segment Analysis
225
Length Tuning Equation Derivation
226
Bus Length Tuning Methodology
228
Processor Bus Tuning
228
Compensating for Package Trace Length Differences
228
Length Matching Equation
229
System Bus Length Matching Example
231
Intel ® Pentium ® M Processor Signal Package Lengths
232
Common Layout Pitfalls
233
Group Like Signals under Bgas
233
Fill Areas under Bgas
235
Signal Parallelism
236
Via Sharing
237
Necking down
239
Signals Crossing Plane Splits
241
Schematic Checklist
243
Processor Schematic Checklist
243
MCH Schematic Checklist
248
Intel ® ICH3-S Schematic Checklist
252
Intel ® 82870P2 (Intel P64H2) Schematic Checklist
260
Intel ® P64H2 Schematic Checklist
260
CK408 Schematic Checklist
265
Layout Checklist
267
Processor Checklist
267
Processor Layout Checklist
267
Intel ® E7501 MCH Layout Checklist
271
Intel ® E7501 Chipset MCH Layout Checklist
271
Intel ® ICH3-S Layout Checklist
275
Intel ® P64H2 Layout Checklist
279
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