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H8S/2197
Hitachi H8S/2197 Manuals
Manuals and User Guides for Hitachi H8S/2197. We have
1
Hitachi H8S/2197 manual available for free PDF download: Hardware Manual
Hitachi H8S/2197 Hardware Manual (1144 pages)
Single-Chip Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 7.4 MB
Table of Contents
Table of Contents
3
Overview
21
Section 1 Overview
22
Overview
22
Internal Block Diagram
28
Pin Arrangement and Functions
29
Pin Arrangement
29
Pin Functions
30
Cpu
37
Overview
37
Features
37
Differences between H8S/2600 CPU and H8S/2000 CPU
38
Differences from H8/300 CPU
38
Differences from H8/300H CPU
39
CPU Operating Modes
40
Address Space
45
Register Configuration
46
Overview
46
General Registers
47
Control Registers
48
Initial Register Values
49
Data Formats
50
General Register Data Formats
50
Memory Data Formats
52
Instruction Set
53
Overview
53
Instructions and Addressing Modes
54
Table of Instructions Classified by Function
55
Basic Instruction Formats
65
Notes on Use of Bit-Manipulation Instructions
66
Addressing Modes and Effective Address Calculation
67
Addressing Mode
67
Effective Address Calculation
70
Processing States
74
Overview
74
Reset State
75
Exception-Handling State
76
Program Execution State
77
Power-Down State
78
Basic Timing
79
On-Chip Memory (ROM, RAM)
79
On-Chip Supporting Module Access Timing
80
MCU Operating Modes
81
Overview
81
Operating Mode Selection
81
Register Configuration
81
Register Descriptions
82
Mode Control Register (MDCR)
82
System Control Register (SYSCR)
82
Operating Mode (Mode 1)
83
Address Map in each Operating Mode
84
Power-Down State
86
Overview
86
Register Configuration
90
Standby Control Register (SBYCR)
90
Low-Power Control Register (LPWRCR)
93
Timer Register a (TMA)
95
Module Stop Control Register (MSTPCR)
96
Medium-Speed Mode
97
Sleep Mode
98
Clearing Sleep Mode
98
Module Stop Mode
99
Standby Mode
100
Clearing Standby Mode
100
Setting Oscillation Settling Time after Clearing Standby Mode
100
Watch Mode
102
Clearing Watch Mode
102
Subsleep Mode
103
Clearing Subsleep Mode
103
Subactive Mode
104
Clearing Subactive Mode
104
Direct Transition
105
Overview of Direct Transition
105
Exception Handling
106
Overview
106
Exception Handling Types and Priority
106
Exception Handling Operation
107
Exception Sources and Vector Table
107
Reset
109
Overview
109
Reset Sequence
109
Interrupts after Reset
110
Interrupts
111
Trap Instruction
112
Stack Status after Exception Handling
113
Notes on Use of the Stack
114
Section 6 Interrupt Controller
115
Overview
115
Features
115
Block Diagram
116
Pin Configuration
117
Register Configuration
117
System Control Register (SYSCR)
117
Interrupt Control Registers a to D (ICRA to ICRD)
119
IRQ Enable Register (IENR)
120
IRQ Edge Select Registers (IEGR)
121
IRQ Status Register (IRQR)
122
Port Mode Register (PMR1)
123
Interrupt Sources
124
External Interrupts
124
Internal Interrupts
125
Interrupt Exception Vector Table
126
Interrupt Operation
129
Interrupt Control Modes and Interrupt Operation
129
Interrupt Control Mode 0
131
Interrupt Control Mode 1
132
Interrupt Exception Handling Sequence
136
Interrupt Response Times
137
Usage Notes
138
Contention between Interrupt Generation and Disabling
138
Instructions that Disable Interrupts
139
Interrupts During Execution of EEPMOV Instruction
139
Rom
140
Overview
140
Block Diagram
140
Overview of Flash Memory
141
Features
141
Block Diagram
142
Flash Memory Operating Modes
143
Pin Configuration
147
Register Configuration
147
Flash Memory Register Descriptions
148
Flash Memory Control Register 1 (FLMCR1)
148
Flash Memory Control Register 2 (FLMCR2)
151
Erase Block Register 1 (EBR1)
154
Erase Block Register 2 (EBR2)
154
Serial/Timer Control Register (STCR)
155
On-Board Programming Modes
157
Boot Mode
158
User Program Mode
163
Programming/Erasing Flash Memory
164
Program Mode (N=1 When the Target Address Range Is H'00000 to H'3FFFF and N=2 When the Target Address Range Is H'40000 to H'47FFF)
164
Program-Verify Mode
165
Erase Mode (N = 1 When the Target Address Range Is H'00000 to H'3FFFF and N = 2 When the Target Address Range Is H'40000 to H'47FFF)
167
Erase-Verify Mode (N = 1 When the Target Address Range Is H'00000 to H'3FFFF and N = 2 When the Target Address Range Is H'40000 to H'47FFF)
169
Flash Memory Protection
170
Hardware Protection
170
Software Protection
171
Error Protection
172
Interrupt Handling When Programming/Erasing Flash Memory
173
Flash Memory Writer Mode
174
Writer Mode Setting
174
Socket Adapters and Memory Map
174
Writer Mode Operation
175
Memory Read Mode
176
Auto-Program Mode
179
Auto-Erase Mode
181
Status Read Mode
182
Status Polling
184
Writer Mode Transition Time
185
Notes on Memory Programming
185
Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
186
Ram
187
Overview
187
Block Diagram
187
Clock Pulse Generator
188
Overview
188
Block Diagram
188
Register Configuration
188
Register Descriptions
189
Standby Control Register (SBYCR)
189
Low-Power Control Register (LPWRCR)
190
Oscillator
191
Connecting a Crystal Resonator
191
External Clock Input
193
Duty Adjustment Circuit
196
Medium-Speed Clock Divider
196
Bus Master Clock Selection Circuit
196
Subclock Oscillator Circuit
197
Connecting 32.768 Khz Crystal Resonator
197
When Subclock Is Not Needed
198
Subclock Waveform Shaping Circuit
198
Notes on the Resonator
198
Section 10 I/O Port
199
Overview
199
Port Functions
199
Port Input
199
MOS Pull-Up Transistors
202
Port 0
203
Overview
203
Register Configuration
204
Pin Functions
205
Pin States
205
Port 1
206
Overview
206
Port 2
206
Register Configuration
206
Pin Functions
210
Port 3
212
Overview
212
Register Configuration
212
Pin Functions
215
Pin States
217
Port 4
218
Overview
218
Register Configuration
218
Pin Functions
222
Pin States
225
Port 6
232
Overview
232
Register Configuration
233
Pin Functions
239
Operation
240
Pin States
241
Port 7
242
Overview
242
Register Configuration
243
Pin Functions
248
Operation
249
Pin States
250
Port 8
251
Overview
251
Register Configuration
252
Pin Functions
258
Pin States
260
Section 11 Timer a
261
Overview
261
Features
261
Block Diagram
262
Register Configuration
262
Register Descriptions
263
Timer Mode Register a (TMA)
263
Timer Counter a (TCA)
265
Module Stop Control Register (MSTPCR)
265
Operation
266
Operation as the Interval Timer
266
Operation as Clock Timer
266
Initializing the Counts
266
Section 12 Timer B
267
Overview
267
Features
267
Block Diagram
267
Pin Configuration
268
Register Configuration
268
Timer Mode Register B (TMB)
268
Timer Counter B (TCB)
271
Timer Load Register B (TLB)
271
Port Mode Register a (PMRA)
272
Module Stop Control Register (MSTPCR)
273
Operation
274
Operation as the Interval Timer
274
Operation as the Auto Reload Timer
274
Event Counter
274
Section 13 Timer J
275
Overview
275
Features
275
Block Diagram
275
Pin Configuration
277
Register Configuration
277
Timer Mode Register J (TMJ)
277
Timer J Control Register (TMJC)
281
Timer J Status Register (TMJS)
284
Timer Counter J (TCJ)
285
Timer Counter K (TCK)
285
Timer Load Register J (TLJ)
286
Timer Load Register K (TLK)
286
Module Stop Control Register (MSTPCR)
287
Operation
288
8-Bit Reload Timer (TMJ-1)
288
8-Bit Reload Timer (TMJ-2)
288
Remote Controlled Data Transmission
289
TMJ-2 Expansion Function
292
Section 14 Timer L
293
Overview
293
Features
293
Block Diagram
294
Register Configuration
295
Register Descriptions
296
Timer L Mode Register (LMR)
296
Linear Time Counter (LTC)
298
Reload/Compare Match Register (RCR)
298
Module Stop Control Register (MSTPCR)
299
Operation
300
Compare Match Clear Operation
300
Section 15 Timer R
302
Overview
302
Features
302
Block Diagram
302
Pin Configuration
304
Register Configuration
304
Register Descriptions
305
Timer R Mode Register 1 (TMRM1)
305
Timer R Mode Register 2 (TMRM2)
307
Timer R Control/Status Register (TMRCS)
310
Timer R Capture Register 1 (TMRCP1)
312
Timer R Capture Register 2 (TMRCP2)
313
Timer R Load Register 1 (TMRL1)
313
Timer R Load Register 2 (TMRL2)
314
Timer R Load Register 3 (TMRL3)
314
Module Stop Control Register (MSTPCR)
315
Operation
316
Reload Timer Counter Equipped with Capturing Function TMRU-1
316
Reload Timer Counter Equipped with Capturing Function TMRU-2
317
Reload Counter Timer TMRU-3
317
Mode Identification
318
Reeling Controls
318
Acceleration and Braking Processes of the Capstan Motor
318
Slow Tracking Mono-Multi Function
319
Interrupt Cause
321
Settings for Respective Functions
322
Mode Identification
322
Reeling Controls
323
Slow Tracking Mono-Multi Function
323
Acceleration and Braking Processes of the Capstan Motor
324
Section 16 Timer X1
326
Overview
326
Features
326
Block Diagram
327
Pin Configuration
328
Register Configuration
329
Register Descriptions
330
Free Running Counter (FRC)
330
Output Comparing Registers a and B (OCRA and OCRB)
331
Input Capture Registers a through D (ICRA through ICRD)
332
Timer Interrupt Enabling Register (TIER)
334
Timer Control/Status Register X (TCSRX)
337
Timer Control Register X (TCRX)
341
Timer Output Comparing Control Register (TOCR)
343
Module Stop Control Register (MSTPCR)
345
Operation
346
Operation of Timer X1
346
Counting Timing of the FRC
347
Output Comparing Signal Outputting Timing
348
FRC Clearing Timing
348
Input Capture Signal Inputting Timing
349
Input Capture Flag (ICFA through ICFD) Setting up Timing
350
Output Comparing Flag (OCFA and OCFB) Setting up Timing
351
Overflow Flag (CVF) Setting up Timing
351
Operation Mode of Timer X1
352
Interrupt Causes
353
Exemplary Uses of Timer X1
354
Precautions When Using Timer X1
355
Competition between Writing and Clearing with the FRC
355
Competition between Writing and Counting up with the FRC
356
Competition between Writing and Comparing Match with the OCR
357
Changing over the Internal Clocks and Counter Operations
358
Section 17 Watchdog Timer (WDT)
360
Overview
360
Features
360
Block Diagram
361
Register Configuration
362
Register Descriptions
363
Watchdog Timer Counter (WTCNT)
363
Watchdog Timer Control/Status Register (WTCSR)
363
System Control Register (SYSCR)
366
Notes on Register Access
367
Operation
368
Watchdog Timer Operation
368
Interval Timer Operation
369
Timing of Setting of Overflow Flag (OVF)
370
Interrupts
371
Usage Notes
371
Contention between Watchdog Timer Counter (WTCNT) Write and Increment
371
Changing Value of CKS2 to CKS0
372
Switching between Watchdog Timer Mode and Interval Timer Mode
372
Section 18 8-Bit PWM
373
Overview
373
Features
373
Block Diagram
373
Pin Configuration
374
Register Configuration
374
Register Descriptions
375
8-Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)
375
8-Bit PWM Control Register (PW8CR)
376
Port Mode Register 3 (PMR3)
377
Module Stop Control Register (MSTPCR)
378
8-Bit PWM Operation
379
Section 19 12-Bit PWM
380
Overview
380
Features
380
Block Diagram
381
Pin Configuration
382
Register Configuration
382
Register Descriptions
383
12-Bit PWM Control Registers (CPWCR, DPWCR)
383
12-Bit PWM Data Registers (DPWDR, CPWDR)
386
Operation
387
Output Waveform
387
Section 20 14-Bit PWM
389
Overview
389
Features
389
Block Diagram
390
Pin Configuration
390
Register Configuration
391
Register Descriptions
392
PWM Control Register (PWCR)
392
PWM Data Registers U and L (PWDRU, PWDRL)
393
Module Stop Control Register (MSTPCR)
394
14-Bit PWM Operation
395
Section 21 Prescalar Unit
396
Overview
396
Features
396
Block Diagram
397
Pin Configuration
398
Register Configuration
398
Registers
399
Input Capture Register 1 (ICR1)
399
Prescalar Unit Control/Status Register (PCSR)
399
Port Mode Register 1 (PMR1)
402
Noise Cancel Circuit
403
Operation
403
Prescalar S (PSS)
403
Prescalar W (PSW)
404
Stable Oscillation Wait Time Count
404
8-Bit PWM
405
8-Bit Input Capture Using ,& Pin
405
Frequency Division Clock Output
405
Section 22 Serial Communication Interface 1 (SCI1)
406
Overview
406
Features
406
Block Diagram
408
Pin Configuration
409
Register Configuration
409
Register Descriptions
410
Receive Shift Register 1 (RSR1)
410
Receive Data Register 1 (RDR1)
410
Transmit Shift Register 1 (TSR1)
411
Transmit Data Register 1 (TDR1)
411
Serial Mode Register 1 (SMR1)
412
Serial Control Register 1 (SCR1)
415
Serial Status Register 1 (SSR1)
419
Bit Rate Register 1 (BRR1)
422
Serial Interface Mode Register 1 (SCMR1)
429
Module Stop Control Register (MSTPCR)
430
Operation
431
Overview
431
Operation in Asynchronous Mode
433
Multiprocessor Communication Function
443
Operation in Synchronous Mode
451
SCI Interrupts
459
Usage Notes
460
Section 23 I C Bus Interface (IIC)
467
Overview
467
Features
467
Block Diagram
468
Pin Configuration
469
Register Configuration
470
Register Descriptions
471
C Bus Data Register (ICDR)
471
Slave Address Register (SAR)
474
Second Slave Address Register (SARX)
476
C Bus Mode Register (ICMR)
477
C Bus Control Register (ICCR)
481
C Bus Status Register (ICSR)
488
Serial/Timer Control Register (STCR)
492
DDC Switch Register (DDCSWR)
493
Module Stop Control Register (MSTPCR)
496
Operation
497
C Bus Data Format
497
Master Transmit Operation
498
Master Receive Operation
502
Slave Receive Operation
504
Slave Transmit Operation
507
IRIC Setting Timing and SCL Control
508
Automatic Switching from Formatless Transfer to I
510
C Bus Format Transfer
510
Noise Canceler
511
Sample Flowcharts
511
23.3.10 Initializing Internal Status
515
Usage Notes
517
Section 24 A/D Converter
521
Overview
521
Features
521
Block Diagram
522
Pin Configuration
523
Register Configuration
524
Register Descriptions
525
Software-Triggered A/D Result Register (ADR)
525
Hardware-Triggered A/D Result Register (AHR)
525
A/D Control Register (ADCR)
526
A/D Control/Status Register (ADCSR)
529
Trigger Select Register (ADTSR)
532
Port Mode Register 0 (PMR0)
532
Module Stop Control Register (MSTPCR)
533
Interface to Bus Master
534
Operation
535
Software-Triggered A/D Conversion
535
Hardware- or External-Triggered A/D Conversion
536
Interrupt Sources
537
Section 25 Address Trap Controller (ATC)
538
Overview
538
Features
538
Block Diagram
538
Register Configuration
539
Register Descriptions
539
Address Trap Control Register (ATCR)
539
Trap Address Register 2 to 0 (TAR2 to TAR0)
541
Precautions in Usage
542
Basic Operations
542
Enabling
544
Bcc Instruction
544
BSR Instruction
548
JSR Instruction
549
JMP Instruction
551
RTS Instruction
552
SLEEP Instruction
553
Competing Interrupt
557
Section 26 Servo Circuits
561
Overview
561
Functions
561
Block Diagram
563
Servo Port
563
Overview
563
Pin Configuration
566
Register Configuration
567
Register Description
567
DFG/DPG Input Signals
571
Reference Signal Generators
572
Overview
572
Block Diagram
572
Register Configuration
574
Register Description
575
Operation
580
HSW (Head-Switch) Timing Generator
595
Overview
595
Block Diagram
595
HSW Timing Generator Configuration
597
Register Configuration
598
Register Description
598
Operation
612
Interrupts
618
Cautions
619
High-Speed Switching Circuit for Four-Head Special Playback
620
Overview
620
Block Diagram
620
Pin Configuration
621
Register Description
621
Drum Speed Error Detector
624
Overview
624
Block Diagram
624
Register Configuration
626
Register Description
627
Operation
632
Drum Phase Error Detector
635
Overview
635
Block Diagram
636
Register Configuration
637
Register Description
638
Operation
641
Phase Comparison
643
Capstan Speed Error Detector
644
Overview
644
Block Diagram
645
Register Configuration
646
Register Description
647
Operation
652
Capstan Phase Error Detector
654
Overview
654
Block Diagram
654
Register Configuration
656
Register Description
657
Operation
660
X-Value and Tracking Adjustment Circuit
662
26.10.1 Overview
662
26.10.2 Block Diagram
662
26.10.3 Register Description
664
Digital Filters
667
26.11.1 Overview
667
26.11.2 Block Diagram
668
26.11.3 Arithmetic Buffer
670
Register Configuration
671
26.11.5 Register Description
672
26.11.6 Filter Characteristics
680
26.11.7 Operations in Case of Transient Response
682
26.11.8 Initialization of Z
682
Additional V Signal Generator
684
26.12.1 Overview
684
Pin Configuration
685
Register Configuration
685
26.12.4 Register Description
685
26.12.5 Additional V Pulse Signal
687
CTL Circuit
690
26.13.1 Overview
690
26.13.2 Block Diagram
691
Pin Configuration
692
Register Configuration
692
26.13.5 Register Description
693
26.13.6 Operation
707
26.13.7 CTL Input Section
710
26.13.8 Duty Discriminator
713
26.13.9 CTL Output Section
719
26.13.10 Trapezoid Waveform Circuit
722
26.13.11 Note on CTL Interrupt
723
26.14.1 Overview
724
26.14.4 DFG Noise Removal Circuit
737
Sync Signal Detector
739
26.15.1 Overview
739
26.15.2 Block Diagram
740
Pin Configuration
741
Register Configuration
741
26.15.5 Register Description
742
26.15.6 Noise Detection
750
26.15.7 Activation of the Sync Signal Detector
753
Servo Interrupt
754
26.16.1 Overview
754
26.16.2 Register Configuration
754
26.16.3 Register Description
754
Section 27 Sync Separator for OSD and Data Slicer
762
Overview
762
Features
763
Block Diagram
763
Pin Configuration
765
Register Configuration
765
Register Description
766
Sync Separation Input Mode Register (SEPIMR)
766
Sync Separation Control Register (SEPCR)
770
Sync Separation AFC Control Register (SEPACR)
773
Horizontal Sync Signal Threshold Register (HVTHR)
775
Vertical Sync Signal Threshold Register (VVTHR)
778
Field Detection Window Register (FWIDR)
780
H Complement and Mask Timing Register (HCMMR)
782
Noise Detection Counter (NDETC)
784
Noise Detection Level Register (NDETR)
785
Data Slicer Detection Window Register (DDETWR)
786
Internal Sync Frequency Register (INFRQR)
788
Operation
789
Selecting Source Signals for Sync Separation
789
Vsync Separation
795
Hsync Separation
796
Field Detection
797
Noise Detection
797
Automatic Frequency Controller (AFC)
798
Module Stop Control Register (MSTPCR)
802
Section 28 Data Slicer
803
Overview
803
Features
803
Block Diagram
804
Pin Configuration
805
Register Configuration
806
Data Slicer Use Conditions
806
Register Description
807
Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD)
807
Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)
811
Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4)
812
Slice Data Registers 1 to 4 (SDATA1 to SDATA4)
815
Module Stop Control Register (MSTPCR)
816
Monitor Output Setting Register (DOUT)
817
Operation
818
Slice Line Specification
818
Slice Sequence
821
Section 29 On-Screen Display (OSD)
822
Overview
822
Features
822
Block Diagram
824
Pin Configuration
825
Register Configuration
826
TV Formats and Display Modes
827
Description of Display Functions
827
Superimposed Mode and Text Display Mode
827
Character Configuration
828
On-Screen Display Configuration
829
Settings in Character Units
830
Character Colors
830
Halftones/Cursors
831
Blinking
832
Button Display
833
Character Data ROM (OSDROM)
834
Display Data RAM (OSDRAM)
836
Settings in Row Units
841
Button Patterns
841
Display Enlargement
841
Character Brightness
841
Cursor Color, Brightness, Halftone Levels
841
Row Registers (Clinen, N = Rows 1 to 12)
843
Settings in Screen Units
848
Display Positions
848
Turning the OSD Display on and off
849
Display Method
849
Blinking Period
849
Borders
850
Background Color and Brightness
850
Character, Cursor, and Background Chroma Saturation
850
Display Position Registers (HPOS and VPOS)
851
Screen Control Register (DCNTL)
853
Other Settings
858
Display Data RAM Control
858
Timing of OSD Display Updates Using Register Rewriting
858
4Fsc/2Fsc
858
OSDV Interrupts
858
OSD Format Register (DFORM)
859
Digital Output
863
R, G, and B Outputs
863
YCO and YBO Outputs
866
Digital Output Specification Register (DOUT)
867
Module Stop Control Register (MTSTPCR)
869
Notes on OSD Font Creation
871
Note 1 on Font Creation (Font Width)
871
Note 2 on Font Creation (Borders)
871
Note 3 on Font Creation (Blinking)
873
Note 4 on Font Creation (Buttons)
874
OSD Oscillator, AFC, and Dot Clock
875
Sync Signals
875
AFC Circuit
875
Dot Clock
875
4/2Fsc
876
OSD Operation in CPU Operation Modes
878
Character Data ROM (OSDROM) Access by CPU
879
Serial Timer Control Register (STCR)
879
Section 30 Electrical Characteristics
880
Absolute Maximum Ratings
880
Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
881
DC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
881
Allowable Output Currents of HD6432199, HD6432198, HD6432197, and HD6432196
888
AC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
889
Serial Interface Timing of HD6432199, HD6432198, HD6432197, and HD6432196
892
A/D Converter Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
896
Servo Section Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
897
OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196
899
Electrical Characteristics of HD64F2199
903
DC Characteristics of HD64F2199
903
A/D Converter Characteristics of HD64F2199
918
Servo Section Electrical Characteristics of HD64F2199
919
OSD Electrical Characteristics of HD64F2199
921
Appendix A Instruction Set
925
Instructions
925
Instruction Codes
936
Operation Code Map
946
Number of Execution States
950
Bus Status During Instruction Execution
960
Change of Condition Codes
974
Appendix B Internal I/O Registers
979
Addresses
979
Function List
988
Bus Interface
1070
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