ARTERY AT32F435VGT7 Manuals

Manuals and User Guides for ARTERY AT32F435VGT7. We have 2 ARTERY AT32F435VGT7 manuals available for free PDF download: Reference Manual

ARTERY AT32F435VGT7 Reference Manual (708 pages)

ARM-based 32-bit Cortex-M4F MCU+FPU with 256 to 4032 KB Flash, sLib, dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23 communication interfaces

Brand: ARTERY | Category: Computer Hardware | Size: 10.51 MB

Table of Contents
2
System Architecture
43
Figure 1-1 AT32F435/437 Series Microcontrollers System Architecture
44
System Overview
45
ARM Cortex
45
TM -M4F Processor
45
Busmatrix
45
Figure 1-2 Internal Block Diagram of Cortex ® -M4F
45
Figure 1-3 Internal Block Diagram of AHB Busmatrix
46
Bit Band
47
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image a
47
Figure 1-5 Comparison between Bit-Band Region and Its Alias Region: Image B
47
Table 1-1 Bit-Band Address Mapping in SRAM
48
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
48
Interrupt and Exception Vectors
49
Table 1-3 AT32F435/437 Series Vector Table
49
System Tick (Systick)
52
Reset
53
Figure 1-6 Reset Process
53
Figure 1-7 Example of MSP and PC Initialization
54
List of Abbreviations for Registers
55
Device Characteristics Information
55
Flash Memory Size Register
55
Device Electronic Signature
55
Table 1-4 List of Abbreviations for Registers
55
Table 1-5 List of Abbreviations for Registers
55
Memory Resources
56
Internal Memory Address Map
56
Flash Memory
56
Figure 2-1AT32F435/437 Address Mapping
56
SRAM Memory
59
Peripheral Address Map
59
Table 2-1 Peripheral Boundary Address
59
Power Control (PWC)
62
Introduction
62
Main Features
62
Por/Lvr
62
Figure 3-1 Block Diagram of each Power Supply
62
Power Voltage Monitor (PVM)
63
Power Domain
63
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
63
Figure 3-3 PVM Threshold and Output
63
Power Saving Modes
64
PWC Registers
66
Table 3-1 PW Register Map and Reset Values
66
Power Control Register (PWC_CTRL)
67
Power Control/Status Register (PWC_CTRLSTS)
67
LDO Output Voltage Select Register (PWC_LDOOV)
68
Clock and Reset Manage (CRM)
69
Clock
69
Clock Sources
69
Figure 4-1 AT32F435/437 Clock Tree
69
System Clock
70
Peripheral Clock
70
Clock Fail Detector
71
Auto Step-By-Step System Clock Switch
71
Clock Output
71
Interrupts
71
Reset
71
System Reset
71
Battery Powered Domain Reset
72
CRM Registers
72
Figure 4-2 System Reset Circuit
72
Table 4-1 CRM Register Map and Reset Values
72
Clock Control Register (CRM_CTRL)
73
PLL Clock Configuration Register (CRM_PLLCFG)
74
Clock Configuration Register (CRM_CFG)
75
Clock Interrupt Register (CRM_CLKINT)
77
APB Peripheral Reset Register1 (CRM_APBRST1)
78
APB Peripheral Reset Register2 (CRM_APBRST2)
79
APB Peripheral Reset Register3 (CRM_APBRST3)
79
APB1 Peripheral Reset Register (CRM_APB1RST)
79
APB2 Peripheral Reset Register (CRM_APB2RST)
81
APB Peripheral Clock Enable Register1 (CRM_AHBEN1)
82
APB Peripheral Clock Enable Register2 (CRM_AHBEN2)
83
APB1 Peripheral Clock Enable Register3 (CRM_AHBEN3)
83
APB1 Peripheral Clock Enable Register (CRM_AHB1EN)
83
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
85
APB Peripheral Clock Enable in Low Power Mode Register1
86
(Crm_Ahblpen1)
86
APB Peripheral Clock Enable in Low Power Mode Register2
87
(Crm_Ahblpen2)
87
APB Peripheral Clock Enable in Low Power Mode Register3
88
(Crm_Ahblpen3)
88
APB1 Peripheral Clock Enable in Low Power Mode Register
88
(Crm_Ahb1Lpen)
88
APB2 Peripheral Clock Enable in Low Power Mode Register
89
(Crm_Ahb2Lpen)
89
Battery Powered Domain Control Register (CRM_BPDC)
90
Control/Status Register (CRM_CTRLSTS)
91
Additional Register1 (CRM_MISC1)
92
Additional Register2 (CRM_MISC2)
93
Flash Memory Controller (FLASH)
94
FLASH Introduction
94
Table 5-1 Flash Memory Architecture(4032 K)
94
Table 5-2 Flash Memory Architecture(1024 K)
95
Table 5-3 Flash Memory Architecture(256 K)
95
Table 5-4 User System Data Area
96
Table 5-5 Extended System Options
98
Flash Memory Operation
99
Unlock/Lock
99
Erase Operation
99
Figure 5-1 Flash Memory Sector Erase Process
100
Figure 5-2 Flash Memory Block Erase Process
101
Programming Operation
102
Figure 5-3 Flash Memory Mass Erase Process
102
Read Operation
103
User System Data Area Operation
103
Unlock/Lock
103
Figure 5-4 Flash Memory Programming Process
103
Erase Operation
104
Figure 5-5 System Data Area Erase Process
104
Programming Operation
105
Figure 5-6 System Data Area Programming Process
105
Read Operation
106
Flash Memory Protection
106
Access Protection
106
Erase/Program Protection
106
Special Functions
106
Security Library Settings
106
Table 5-6 Flash Memory Access Limit
106
Flash Memory Registers
107
Flash Performance Select Register (FLASH_PSR)
108
Table 5-7 Flash Memory Interface-Register Map and Reset Value
108
Flash Unlock Register (FLASH_UNLOCK)
109
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
109
Flash Status Register (FLASH_STS)
109
Flash Control Register (FLASH_CTRL)
109
Flash Address Register (FLASH_ADDR)
110
User System Data Register (FLASH_USD)
110
Erase/Program Protection Status Register0 (FLASH_EPPS0)
111
Erase/Program Protection Status Register1 (FLASH_EPPS1)
111
Flash Unlock Register2 (FLASH
111
Flash Status Register2 (FLASH_STS2)
111
Flash Control Register2 (FLASH_CTRL2)
111
Flash Address Register2 (FLASH_ADDR2)
112
Flash Continue Read Register (FLASH_CONTR)
112
Flash Divider Register (FLASH_DIVR)
112
Flash Security Library Status Register2 (SLIB_STS2)
113
Flash Security Library Status Register0 (SLIB_STS0)
113
Flash Security Library Status Register1 (SLIB_STS1)
113
Flash Security Library Password Clear Register (SLIB_PWD_CLR)
113
Security Library Additional Status Register (SLIB_MISC_STS)
113
Security Library Password Setting Register (SLIB_SET_PWD)
114
Security Library Address Setting Register0 (SLIB_SET_RANGE0)
114
Security Library Address Setting Register1 (SLIB_SET_RANGE1)
114
Security Library Unlock Register (SLIB_UNLOCK)
115
Flash CRC Calibration Control Register (FLASH_CRC_CTRL)
115
Flash CRC Check Result Register (FLASH_CRC_CHKR)
115
Gpios and IOMUX
116
Introduction
116
Function Overview
116
GPIO Structure
116
GPIO Reset Status
116
Figure 6-1 GPIO Basic Structure
116
General-Purpose Input Configuration
117
Analog Input/Output Configuration
117
General-Purpose Output Configuration
117
I/O Port Protection
117
IOMUX Structure
118
Multiplexed Function Pull-Up/Down Configuration
118
Figure 6-2 IOMUX Structure
118
IOMUX Input/Output
119
Table 6-1 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
119
Table 6-2 Port B Multiplexed Function Configuration with GPIOB_MUX* Register
121
Table 6-3 Port C Multiplexed Function Configuration with GPIOC_MUX* Register
123
Table 6-4 Port D Multiplexed Function Configuration with GPIOD_MUX* Register
125
Table 6-5 Port E Multiplexed Function Configuration with GPIOE_MUX* Register
127
Table 6-6 Port F Multiplexed Function Configuration with GPIOF_MUX* Register
129
Table 6-7 Port G Multiplexed Function Configuration with GPIOG_MUX* Register
131
Peripheral MUX Function Configuration
133
IOMUX Map Priority
133
Table 6-8 Port H Multiplexed Function Configuration with GPIOH_MUX* Register
133
Table 6-9 Pins Owned by Hardware
133
External Interrupt/Wake-Up Lines
134
GPIO Registers
134
GPIO Configuration Register (Gpiox_Cfgr) (X=A..h
134
GPIO Output Mode Register (Gpiox_Omode) (X=A..h
134
Table 6-10 GPIO Register Map and Reset Values
134
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..h
135
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..h
135
GPIO Input Register (Gpiox_Idh) (X=A..h
135
GPIO Output Register (Gpiox_Idh) (X=A..h
135
GPIO Set/Clear Register (Gpiox_Scr) (X=A..h
135
GPIO Write Protection Register (Gpiox_Wpr) (X=A..h
136
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
136
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
137
GPIO Port Bit Clear Register (Gpiox_Clr) (X=A
137
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
137
System Configuration Controller (SCFG)
138
Introduction
138
IOMUX Registers
138
SCFG Configuration Register1 (SCFG_CFG1)
138
Table 7-1 SCFG Register Map and Reset Values
138
SCFG Configuration Register2 (SCFG_CFG2)
139
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)
140
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)
141
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)
142
SCFG Ultra High Sourcing/Sinking Strength (SCFG_UHDRV)
144
External Interrupt/Event Controller (EXINT)
146
EXINT Introduction
146
Function Overview and Configuration Procedure
146
Figure 8-1 External Interrupt/Event Controller Block Diagram
146
EXINT Registers
147
Interrupt Enable Register (EXINT_INTEN)
147
Event Enable Register (EXINT_EVTEN)
147
Polarity Configuration Register1 (EXINT_ POLCFG1)
147
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
147
Polarity Configuration Register2 (EXINT_ POLCFG2)
148
Software Trigger Register (EXINT_ SWTRG)
148
Interrupt Status Register (EXINT_ INTSTS)
148
DMA Controller (DMA)
149
Introduction
149
Main Features
149
Figure 9-1 DMA Block Diagram
149
Function Overview
150
DMA Configuration
150
Handshake Mechanism
150
Arbiter
151
Programmable Data Transfer Width
151
Figure 9-2 Re-Arbitrate after Request/Acknowledge
151
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
151
Errors
152
Interrupts
152
DMA Multiplexer (DMAMUX)
152
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
152
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
152
Table 9-1 DMA Error Event
152
Table 9-2 DMA Interrupt Requests
152
DMAMUX Functional Overview
153
Figure 9-6 DMAMUX Block Diagram
153
Table 9-3 Flexible DMA1/DMA2 Request Mapping
154
DMAMUX Overflow Interrupts
155
Figure 9-7 DMAMUX Request Synchronized Mode
155
Table 9-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
155
DMA Registers
156
Figure 9-8 DMAMUX Event Generation
156
Table 9-5 DMA Register Map and Reset Value
156
DMA Interrupt Status Register (DMA_STS)
157
DMA Interrupt Flag Clear Register (DMA_CLR)
159
DMA Channel-X Configuration Register (Dma_Cxctrl) (X = 1
161
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X = 1
162
DMAMUX Selection Register (DMA_MUXSEL)
162
DMAMUX Generator X Control Register (Dma_Muxgxctrl) (X = 1
163
DMAMUX Channel Synchronization Status Register
164
DMAMUX Generator Interrupt Status Register (DMA_ MUXGSTS)
164
DMAMUX Generator Interrupt Flga Clear Register (DMA_ MUXGCLR)165
165
CRC Calculation Unit (CRC)
166
CRC Introduction
166
CRC Registers
166
Data Register (CRC_DT)
166
Common Data Register (CRC_CDT)
166
Control Register (CRC_CTRL)
166
Table 10-1 CRC Register Map and Reset Value
166
Initialization Register (CRC_IDT)
167
C Interface
168
I 2 C Introduction
168
I 2 C Main Features
168
I 2 C Function Overview
168
Figure 11-1 I2C Bus Protocol
168
I 2 C Interface
169
Figure 11-2 I2C Function Block Diagram
169
C Timing Control
171
Figure 11-3 Setup and Hold Time
171
Data Transfer Management
172
Table 11-1 I C Timing Specifications
172
C Master Communication Flow
173
Table 11-2 I 2 C Configuration Table
173
Figure 11-4 I 2 C Master Transmission Flow
175
Figure 11-5 Transfer Sequence of I
176
Figure 11-6 I 2 C Master Receive Flow
176
Figure 11-7 Transfer Sequence of I
177
Figure 11-8 10-Bit Address Read Access When READH10=1
177
Figure 11-9 10-Bit Address Read Access When READH10=0
177
C Slave Communication Flow
178
Figure 11-10 I 2 C Slave Transmission Flow
180
Figure 11-11 I 2 C Slave Transmission Timing
180
Figure 11-12 I 2 C Slave Receive Flow
181
Figure 11-13 I 2 C Slave Receive Timing
181
Smbus
182
Table 11-3 Smbus Timeout Specification
183
Table 11-4 Smbus Timeout Detection Configuration
183
Smbus Master Communication Flow
184
Table 11-5 Smbus Mode Configuration
184
Figure 11-14 Smbus Master Transmission Flow
186
Figure 11-15 Smbus Master Transmission Timing
187
Figure 11-16 Smbus Master Receive Flow
187
Smbus Slave Communication Flow
188
Figure 11-17 Smbus Master Receive Timing
188
Figure 11-18 Smbus Slave Transmission Flow
190
Figure 11-19 Smbus Slave Transmission Timing
190
Figure 11-20 Smbus Slave Receive Flow
191
Figure 11-21 Smbus Slave Receive Timing
191
Data Transfer Using DMA
192
Error Management
192
Table 11-6 I 2 C Error Events
192
I 2 C Interrupt Requests
194
I 2 C Debug Mode
194
I 2 C Registers
194
Table 11-7 I 2 C Interrupt Requests
194
Table 11-8 I 2 C Register Map and Reset Values
194
Control Register1 (I2C_CTRL1)
195
Control Register2 (I2C_CTRL2)
196
Address Register1 (I2C_OADDR1)
197
Own Address Register2 (I2C_OADDR2)
197
Timing Register (I2C_CLKCTRL)
197
Timeout Register (I2C_TIMEOUT)
197
Status Register (I2C_STS)
198
Status Clear Register (I2C_CLR)
199
PEC Register (I2C_PEC)
200
Receive Data Register (I2C_RXDT)
200
Transmit Data Register (I2C_TXDT)
200
Universal Synchronous/Asynchronous Receiver/Transmitter
201
Usart
201
USART Introduction
201
Figure 12-1 USART Block Diagram
201
Full-Duplex/Half-Duplex Selector
203
Mode Selector
203
Introduction
203
Configuration Procedure
203
Figure 12-2 BFF and FERR Detection in LIN Mode
204
Figure 12-3 Smartcard Frame Format
204
Figure 12-4 Irda DATA(3/16) - Normal Mode
205
Figure 12-5 Hardware Flow Control
205
USART Frame Format and Configuration
206
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
206
Figure 12-7 8-Bit Format USART Synchronous Mode
206
Figure 12-8 Word Length
207
DMA Transfer Introduction
208
Transmission Using DMA
208
Reception Using DMA
208
Baud Rate Generation
209
Introduction
209
Configuration
209
Table 12-1 Error Calculation for Programmed Baud Rate
209
Transmitter
210
Transmitter Introduction
210
Transmitter Configuration
210
Receiver
211
Receiver Introduction
211
Receiver Configuration
211
Start Bit and Noise Detection
212
Table 12-2 Data Sampling over Start Bit and Noise Detection
212
Tx/Rx Swap
213
Table 12-3 Data Sampling over Valid Data and Noise Detection
213
Interrupt Requests
214
Table 12-4 USART Interrupt Request
214
I/O Pin Control
215
USART Registers
215
Status Register (USART_STS)
215
Table 12-5 USART Register Map and Reset Value
215
Data Register (USART_DT)
216
Baud Rate Register (USART_BAUDR)
217
Control Register1 (USART_CTRL1)
217
Control Register2 (USART_CTRL2)
218
Control Register3 (USART_CTRL3)
219
Guard Time and Divider Register (USART_GDIV)
220
Serial Peripheral Interface (SPI)
221
SPI Introduction
221
Function Overview
221
SPI Description
221
Figure 13-1 SPI Block Diagram
221
Full-Duplex/Half-Duplex Selector
222
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
222
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
223
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
223
Chip Select Controller
224
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
224
SPI_SCK Controller
225
Crc
225
DMA Transfer
226
TI Mode
226
Transmitter
227
Receiver
227
Motorola Mode
228
Figure 13-6 Master Full-Duplex Communications
228
Figure 13-7 Slave Full-Duplex Communications
229
Figure 13-8 Master Half-Duplex Transmit
229
Figure 13-9 Slave Half-Duplex Receive
229
TI Mode
230
Figure 13-10 Slave Half-Duplex Transmit
230
Figure 13-11 Master Half-Duplex Receive
230
Figure 13-12 TI Mode Continous Transfer
230
Interrupts
231
IO Pin Control
231
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
231
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
231
Figure 13-15 SPI Interrupts
231
Precautions
232
I 2 S Functional Description
232
S Introduction
232
Figure 13-16 I 2 S Block Diagram
232
I 2 S Full-Duplex
233
Operating Mode Selector
233
Figure 13-17 I 2 S Full-Duplex Structure
233
Figure 13-18 I 2 S Slave Device Transmission
233
Figure 13-19 I 2 S Slave Device Reception
234
Figure 13-20 I 2 S Master Device Transmission
234
Figure 13-21 I 2 S Master Device Reception
234
Audio Protocol Selector
235
I2S_CLK Controller
236
Figure 13-22 CK & MCK Source in Master Mode
236
Table 13-1 Audio Frequency Precision Using System Clock
236
DMA Transfer
238
Transmitter/Receiver
238
I2S Communication Timings
239
Figure 13-23 Audio Standard Timings
239
Interrupts
240
IO Pin Control
240
Figure 13-24 I S Interrupts
240
SPI Registers
241
SPI Control Register1 (SPI_CTRL1)
241
Mode
241
Table 13-2 SPI Register Map and Reset Value
241
SPI Control Register2 (SPI_CTRL2)
242
SPI Status Register (SPI_STS)
243
SPI Data Register (SPI_DT)
244
SPICRC Register (SPI_CPOLY)
244
Mode)
244
Spirxcrc Register (SPI_RCRC)
244
Spitxcrc Register (SPI_TCRC)
244
SPI_I2S Register (SPI_I2SCTRL)
244
SPI_I2S Prescaler Register (SPI_I2SCLKP)
245
Timer
246
Table 14-1 TMR Functional Comparison
246
Basic Timer (TMR6 and TMR7)
247
TMR6 and TMR7 Introduction
247
TMR6 and TMR7 Main Features
247
TMR6 and TMR7 Function Overview
247
Count Clock
247
Counting Mode
247
Figure 14-1Basic Timer Block Diagram
247
Figure 14-2 Control Circuit with CK_INT Divided by 1
247
Figure 14-3 Counter Structure
248
Figure 14-4 Overflow Event When PRBEN=0
248
Figure 14-5 Overflow Event When PRBEN=1
248
Debug Mode
249
TMR6 and TMR7 Registers
249
Table 14-2 TMR6 and TMR7- Register Table and Reset Value
249
TMR6 and TMR7 Control Register1 (Tmrx_Ctrl1)
250
TMR6 and TMR7 Control Register2 (Tmrx_Ctrl2)
250
TMR6 and TMR7 Dma/Interrupt Enable Register (Tmrx_Iden)
250
TMR6 and TMR7 Interrupt Status Register (Tmrx_Ists)
251
TMR6 and TMR7 Software Event Register (Tmrx_Swevt)
251
TMR6 and TMR7 Counter Value (Tmrx_Cval)
251
TMR6 and TMR7 Division (Tmrx_Div)
251
TMR6 and TMR7 Period Register (Tmrx_Pr)
251
General-Purpose Timer (TMR2 to TMR5)
252
TMR2 to TMR5 Introduction
252
TMR2 to TMR5 Main Features
252
TMR2 to TMR5 Functional Overview
252
Count Clock
252
Table 14-3 Tmrx Internal Trigger Connection
255
Counting Mode
256
TMR Input Function
259
Table 14-4 Couting Direction Versus Encoder Signals
259
TMR Output Function
261
TMR Synchronization
264
Debug Mode
267
Tmrx Registers
267
Table 14-5 Tmrx Register Map and Reset Value
267
TMR2 to TMR5 Control Register1 (Tmrx_Ctrl1)
268
TMR2 to TMR5 Control Register2 (Tmrx_Ctrl2)
269
TMR2 to TMR5 Slave Timer Control Register (Tmrx_Stctrl)
269
TMR2 to TMR5 Dma/Interrupt Enable Register (Tmrx_Iden)
270
TMR2 to TMR5 Interrupt Status Register (Tmrx_Ists)
271
TMR2 to TMR5 Software Event Register (Tmrx_Swevt)
272
TMR2 to TMR5 Channel Mode Register1 (Tmrx_Cm1)
272
TMR2 to TMR5 Channel Mode Register2 (Tmrx_Cm2)
274
TMR2 to TMR5 Channel Control Register (Tmrx_Cctrl)
275
TMR2 to TMR5 Counter Value (Tmrx_Cval)
275
Table 14-6 Standard Cxout Channel Output Control Bit
275
TMR2 to TMR5 Division Value (Tmrx_Div)
276
TMR2 to TMR5 Period Register (Tmrx_Pr)
276
TMR2 to TMR5 Channel 1 Data Register (Tmrx_C1Dt)
276
TMR2 to TMR5 Channel 2 Data Register (Tmrx_C2Dt)
276
TMR2 to TMR5 Channel 3 Data Register (Tmrx_C3Dt)
276
TMR2 to TMR5 Channel 4 Data Register (Tmrx_C4Dt)
277
TMR2 to TMR5 DMA Control Register (Tmrx_Dmactrl)
277
TMR2 to TMR5 DMA Data Register (Tmrx_Dmadt)
277
TMR5 Channel Input Remapping Register (TMR2_RMP)
277
TMR2 Channel Input Remapping Register (TMR5_RMP)
277
General-Purpose Timer (TMR9 to TMR14)
278
TMR9 to TMR14 Introduction
278
TMR9 to TMR14 Main Features
278
TMR9 and TMR12 Main Features
278
TMR10, TMR11, TMR13 and TMR14 Main Features
278
TMR9 to TMR14 Functional Overview
279
Count Clock
279
Table 14-7 Tmrx Internal Trigger Connection
281
Counting Mode
282
TMR Input Function
283
TMR Output Function
286
TMR Synchronization
288
Debug Mode
289
TMR9 and TMR12 Registers
289
TMR9 and TMR12 Control Register1 (Tmrx_Ctrl1)
289
Table 14-8 Tmrx Register Map and Reset Value
289
TMR9 and TMR12 Slave Timer Control Register (Tmrx_Stctrl)
290
TMR9 and TMR12 Dma/Interrupt Enable Register (Tmrx_Iden)
290
TMR9 and TMR12 Interrupt Status Register (Tmrx_Ists)
291
TMR9 and TMR12 Software Event Register (Tmrx_Swevt)
291
TMR9 and TMR12 Channel Mode Register1 (Tmrx_Cm1)
292
TMR9 and TMR12 Channel Control Register (Tmrx_Cctrl)
294
TMR9 and TMR12 Counter Value (Tmrx_Cval)
294
TMR9 and TMR12 Division Value (Tmrx_Div)
294
TMR9 and TMR12 Period Register (Tmrx_Pr)
294
TMR9 and TMR12 Channel 1 Data Register (Tmrx_C1Dt)
294
Table 14-9 Standard Cxout Channel Output Control Bit
294
TMR9 and TMR12 Channel 2 Data Register (Tmrx_C2Dt)
295
TMR10,TMR11, TMR13 and TMR14 Registers
295
TMR10, TMR11, TMR13 and TMR14 Control Register1 (Tmrx_Ctrl1)
295
Table 14-10 Tmrx Register Map and Reset Value
295
TMR10, TMR11, TMR13 and TMR14 Dma/Interrupt Enable Register
296
(Tmrx_Iden)
296
TMR10, TMR11, TMR13 and TMR14 Interrupt Status Register
296
(Tmrx_Ists)
296
TMR10, TMR11, TMR13 and TMR14 Software Event Register
296
(Tmrx_Swevt)
296
TMR10, TMR11, TMR13 and TMR14 Channel Mode Register1
297
(Tmrx_Cm1)
297
TMR10, TMR11, TMR13 and TMR14 Channel Control Register
298
(Tmrx_Cctrl)
298
TMR10, TMR11, TMR13 and TMR14 Counter Value (Tmrx_Cval)
299
TMR10, TMR11, TMR13 and TMR14 Division Value (Tmrx_Div)
299
TMR10, TMR11, TMR13 and TMR14 Period Register (Tmrx_Pr)
299
TMR10, TMR11, TMR13 and TMR14 Channel 1 Data Register
299
Tmrx_C1Dt)
299
Table 14-11 Standard Cxout Channel Output Control Bit
299
Advanced-Control Timers (TMR1,TMR8 and TMR20)
300
TMR1,TMR8 and TMR20 Introduction
300
TMR1,TMR8 and TMR20 Main Features
300
TMR1 and TMR8 Functional Overview
300
Count Clock
300
Table 14-12 Tmrx Internal Trigger Connection
303
Counting Mode
304
Table 14-13 Couting Direction Versus Encoder Signals
307
TMR Input Function
308
TMR Output Function
310
Figure 14-77 Example of PWM Input Mode Configuration
310
Figure 14-78 PWM Input Mode
310
Figure 14-79 Channel Output Stage (Channel 1 to 3)
311
TMR Brake Function
314
TMR Synchronization
316
Debug Mode
317
Figure 14-89 Example of Reset Mode
317
TMR1, TMR8 and TM20 Registers
318
TMR1, TMR8 and TMR20 Control Register1 (Tmrx_Ctrl1)
318
Table 14-14 TMR1 and TMR8 Register Map and Reset Value
318
TMR1, TMR8 and TMR20 Control Register2 (Tmrx_Ctrl2)
319
TMR1, TMR8 and TMR20 Slave Timer Control Register
320
(Tmrx_Stctrl)
320
TMR1, TMR8 and TMR20 Dma/Interrupt Enable Register
321
(Tmrx_Iden)
321
TMR1, TMR8 and TMR20 Interrupt Status Register (Tmrx_Ists)
322
TMR1, TMR8 and TMR20 Software Event Register (Tmrx_Swevt)
323
TMR1, TMR8 and TMR20 Channel Mode Register1 (Tmrx_Cm1)
323
TMR1, TMR8 and TMR20 Channel Mode Register2 (Tmrx_Cm2)
325
TMR1, TMR8 and TMR20 Channel Control Register (Tmrx_Cctrl)
326
Table 14-15 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function
327
TMR1, TMR8 and TMR20 Counter Value (Tmrx_Cval)
328
TMR1, TMR8 and TMR20 Division Value (Tmrx_Div)
328
TMR1, TMR8 and TMR20 Period Register (Tmrx_Pr)
328
TMR1, TMR8 and TMR20 Repetition Period Register (Tmrx_Rpr)
328
TMR1, TMR8 and TMR20 Channel 1 Data Register (Tmrx_C1Dt)
328
TMR1, TMR8 and TMR20 Channel 2 Data Register (Tmrx_C2Dt)
329
TMR1, TMR8 and TMR20 Channel 3 Data Register (Tmrx_C3Dt)
329
TMR1, TMR8 and TMR20 Channel 4 Data Register (Tmrx_C4Dt)
329
TMR1, TMR8 and TMR20 Brake Register (Tmrx_Brk)
329
TMR1, TMR8 and TMR20 DMA Control Register
330
(Tmrx_Dmactrl)
330
TMR1, TMR8 and TMR20 DMA Data Register (Tmrx_Dmadt)
331
TMR1, TMR8 and TMR20 Channel Mode Register3 (Tmrx_ CM3)
331
TMR1, TMR8 and TMR20 Channel 5 Data Register (Tmrx_C5Dt)
331
Window Watchdog Timer (WWDT)
332
WWDT Introduction
332
WWDT Main Features
332
WWDT Functional Overview
332

ARTERY AT32F435VGT7 Reference Manual (714 pages)

ARM-based 32-bit Cortex-M4F MCU+FPU with 256 to 4032 KB Flash, sLib, dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23 communication interfaces

Brand: ARTERY | Category: Computer Hardware | Size: 19.67 MB

Table of Contents
2
System Architecture
44
Figure 1-1 AT32F435/437 Series Microcontrollers System Architecture
45
1.1 System Overview
46
ARM Cortex
46
M4F Processor
46
Busmatrix
46
Figure 1-2 Internal Block Diagram of Cortex ® -M4F
46
Figure 1-3 Internal Block Diagram of AHB Busmatrix
47
Bit Band
48
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image a
48
Figure 1-5 Comparison between Bit-Band Region and Its Alias Region: Image B
48
Table 1-1 Bit-Band Address Mapping in SRAM
49
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
49
Interrupt and Exception Vectors
50
Table 1-3 AT32F435/437 Series Vector Table
50
System Tick (Systick)
53
Reset
54
Figure 1-6 Reset Process
54
Figure 1-7 Example of MSP and PC Initialization
55
1.2 List of Abbreviations for Registers
56
1.3 Device Characteristics Information
56
Flash Memory Size Register
56
Device Electronic Signature
56
Table 1-4 List of Abbreviations for Registers
56
Table 1-5 List of Abbreviations for Registers
56
Memory Resources
57
2.1 Internal Memory Address Map
57
2.2 Flash Memory
57
Figure 2-1 AT32F435/437 Address Mapping
57
2.3 SRAM Memory
60
2.4 Peripheral Address Map
60
Table 2-1 Peripheral Boundary Address
60
Power Control (PWC)
63
3.1 Introduction
63
3.2 Main Features
63
3.3 Por/Lvr
63
Figure 3-1 Block Diagram of each Power Supply
63
Power Voltage Monitor (PVM)
64
3.5 Power Domain
64
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
64
Figure 3-3 PVM Threshold and Output
64
3.6 Power Saving Modes
65
3.7 PWC Registers
67
Table 3-1 PW Register Map and Reset Values
67
Power Control Register (PWC_CTRL)
68
Power Control/Status Register (PWC_CTRLSTS)
68
LDO Output Voltage Select Register (PWC_LDOOV)
69
Clock and Reset Manage (CRM)
70
4.1 Clock
70
Clock Sources
70
Figure 4-1 AT32F435/437 Clock Tree
70
System Clock
71
Peripheral Clock
71
Clock Fail Detector
72
Auto Step-By-Step System Clock Switch
72
Clock Output
72
Interrupts
72
4.2 Reset
72
System Reset
72
Battery Powered Domain Reset
74
4.3 CRM Registers
74
Figure 4-2 System Reset Circuit
74
Table 4-1 CRM Register Map and Reset Values
74
Clock Control Register (CRM_CTRL)
75
PLL Clock Configuration Register (CRM_PLLCFG)
76
Clock Configuration Register (CRM_CFG)
77
Clock Interrupt Register (CRM_CLKINT)
79
APB Peripheral Reset Register1 (CRM_APBRST1)
80
APB Peripheral Reset Register2 (CRM_APBRST2)
81
APB Peripheral Reset Register3 (CRM_APBRST3)
81
APB1 Peripheral Reset Register (CRM_APB1RST)
81
APB2 Peripheral Reset Register (CRM_APB2RST)
83
APB Peripheral Clock Enable Register1 (CRM_AHBEN1)
84
APB Peripheral Clock Enable Register2 (CRM_AHBEN2)
85
APB1 Peripheral Clock Enable Register3 (CRM_AHBEN3)
85
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
85
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
87
4.3.15 APB Peripheral Clock Enable in Low Power Mode Register1
88
(Crm_Ahblpen1)
88
4.3.16 APB Peripheral Clock Enable in Low Power Mode Register2
89
(Crm_Ahblpen2)
89
4.3.17 APB Peripheral Clock Enable in Low Power Mode Register3
90
(Crm_Ahblpen3)
90
4.3.18 APB1 Peripheral Clock Enable in Low Power Mode Register
90
(Crm_Ahb1Lpen)
90
4.3.19 APB2 Peripheral Clock Enable in Low Power Mode Register
91
(Crm_Ahb2Lpen)
91
Battery Powered Domain Control Register (CRM_BPDC)
92
Control/Status Register (CRM_CTRLSTS)
93
Additional Register1 (CRM_MISC1)
94
Additional Register2 (CRM_MISC2)
95
Flash Memory Controller (FLASH)
96
5.1 FLASH Introduction
96
Table 5-1 Flash Memory Architecture (4032 K)
96
Table 5-2 Flash Memory Architecture (1024 K)
97
Table 5-3 Flash Memory Architecture (448 K)
97
Table 5-4 Flash Memory Architecture (256 K)
98
Table 5-5 User System Data Area
98
Table 5-6 Extended System Options
101
5.2 Flash Memory Operation
102
Unlock/Lock
102
Erase Operation
102
Figure 5-1 Flash Memory Sector Erase Process
103
Figure 5-2 Flash Memory Block Erase Process
104
Programming Operation
105
Figure 5-3 Flash Memory Mass Erase Process
105
Read Operation
106
5.3 User System Data Area Operation
106
Unlock/Lock
106
Figure 5-4 Flash Memory Programming Process
106
Erase Operation
107
Figure 5-5 System Data Area Erase Process
107
Programming Operation
108
Figure 5-6 System Data Area Programming Process
108
Read Operation
109
5.4 Flash Memory Protection
109
Access Protection
109
Erase/Program Protection
109
5.5 Special Functions
109
Security Library Settings
109
Table 5-7 Flash Memory Access Limit
109
5.6 Flash Memory Registers
110
Flash Performance Select Register (FLASH_PSR)
111
Table 5-8 Flash Memory Interface-Register Map and Reset Value
111
Flash Unlock Register (FLASH_UNLOCK)
112
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
112
Flash Status Register (FLASH_STS)
112
Flash Control Register (FLASH_CTRL)
112
Flash Address Register (FLASH_ADDR)
113
User System Data Register (FLASH_USD)
113
Erase/Program Protection Status Register0 (FLASH_EPPS0)
114
Erase/Program Protection Status Register1 (FLASH_EPPS1)
114
Flash Unlock Register2 (FLASH_UNLOCK2)
114
Figure 6-1 GPIO Basic Structure
119
Figure 6-2 IOMUX Structure
121
Table 6-1 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
122
Table 6-2 Port B Multiplexed Function Configuration with GPIOB_MUX* Register
124
Table 6-3 Port C Multiplexed Function Configuration with GPIOC_MUX* Register
126
Table 6-4 Port D Multiplexed Function Configuration with GPIOD_MUX* Register
128
Table 6-5 Port E Multiplexed Function Configuration with GPIOE_MUX* Register
130
Table 6-6 Port F Multiplexed Function Configuration with GPIOF_MUX* Register
132
Table 6-7 Port G Multiplexed Function Configuration with GPIOG_MUX* Register
134
Table 6-8 Port H Multiplexed Function Configuration with GPIOH_MUX* Register
136
Table 6-9 Pins Owned by Hardware
136
Table 6-10 GPIO Register Map and Reset Values
137
Table 7-1 SCFG Register Map and Reset Values
141
Figure 8-1 External Interrupt/Event Controller Block Diagram
149
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
150
Figure 9-1 DMA Block Diagram
152
Figure 9-2 Re-Arbitrate after Request/Acknowledge
154
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
154
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
155
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
155
Table 9-1 DMA Error Event
155
Table 9-2 DMA Interrupt Requests
155
Figure 9-6 DMAMUX Block Diagram
156
Table 9-3 Flexible DMA1/DMA2 Request Mapping
157
Figure 9-7 DMAMUX Request Synchronized Mode
158
Table 9-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
158
Figure 9-8 DMAMUX Event Generation
159
Table 9-5 DMA Register Map and Reset Value
159
Figure 10-1 CRC Calculation Unit Block Diagram
169
Figure 10-2 Diagram of Byte Reverse
170
Table 10-1 CRC Register Map and Reset Value
170
Figure 11-1 I C Bus Protocol
172
Figure 11-2 I C Function Block Diagram
173
Figure 11-3 Setup and Hold Time
175
Table 11-1 I C Timing Specifications
176
Table 11-2 I 2 C Configuration Table
177
Figure 11-4 I 2 C Master Transmission Flow
179
Figure 11-5 Transfer Sequence of I
180
Figure 11-6 I 2 C Master Receive Flow
180
Figure 11-7 Transfer Sequence of I
181
Figure 11-8 10-Bit Address Read Access When READH10=1
181
Figure 11-9 10-Bit Address Read Access When READH10=0
181
Figure 11-10 I 2 C Slave Transmission Flow
184
Figure 11-11 I 2 C Slave Transmission Timing
184
Figure 11-12 I 2 C Slave Receive Flow
185
Figure 11-13 I 2 C Slave Receive Timing
185
Table 11-3 Smbus Timeout Specification
187
Table 11-4 Smbus Timeout Detection Configuration
187
Table 11-5 Smbus Mode Configuration
188
Figure 11-14 Smbus Master Transmission Flow
190
Figure 11-15 Smbus Master Transmission Timing
191
Figure 11-16 Smbus Master Receive Flow
191
Figure 11-17 Smbus Master Receive Timing
192
Figure 11-18 Smbus Slave Transmission Flow
194
Figure 11-19 Smbus Slave Transmission Timing
194
Figure 11-20 Smbus Slave Receive Flow
195
Figure 11-21 Smbus Slave Receive Timing
195
Table 11-6 I 2 C Error Events
196
Table 11-7 I 2 C Interrupt Requests
198
Table 11-8 I 2 C Register Map and Reset Values
198
Figure 12-1 USART Block Diagram
205
Figure 12-2 BFF and FERR Detection in LIN Mode
208
Figure 12-3 Smartcard Frame Format
208
Figure 12-4 Irda DATA(3/16) - Normal Mode
209
Figure 12-5 Hardware Flow Control
209
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
210
Figure 12-7 8-Bit Format USART Synchronous Mode
210
Figure 12-8 Word Length
211
Figure 12-9 Stop Bit Configuration
212
Table 12-1 Error Calculation for Programmed Baud Rate
213
Figure 12-10 TDC/TDBE Behavior When Transmitting
215
Table 12-2 Data Sampling over Start Bit and Noise Detection
216
Figure 12-11 Data Sampling for Noise Detection
217
Table 12-3 Data Sampling over Valid Data and Noise Detection
217
Figure 12-12 Tx/Rx Swap
218
Table 12-4 USART Interrupt Request
218
Figure 12-13 USART Interrupt Map Diagram
219
Table 12-5 USART Register Map and Reset Value
219
Figure 13-1 SPI Block Diagram
225
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
226
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
227
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
227
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
228
Figure 13-6 Master Full-Duplex Communications
232
Figure 13-7 Slave Full-Duplex Communications
233
Figure 13-8 Master Half-Duplex Transmit
233
Figure 13-9 Slave Half-Duplex Receive
233
Figure 13-10 Slave Half-Duplex Transmit
234
Figure 13-11 Master Half-Duplex Receive
234
Figure 13-12 TI Mode Continous Transfer
234
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
235
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
235
Figure 13-15 SPI Interrupts
235
Figure 13-16 I 2 S Block Diagram
236
Figure 13-17 I 2 S Full-Duplex Structure
237
Figure 13-18 I 2 S Slave Device Transmission
237
Figure 13-19 I 2 S Slave Device Reception
238
Figure 13-20 I S Master Device Transmission
238
Figure 13-21 I 2 S Master Device Reception
238
Figure 13-22 CK & MCK Source in Master Mode
240
Table 13-1 Audio Frequency Precision Using System Clock
240
Figure 13-23 Audio Standard Timings
243
Figure 13-24 I S Interrupts
244
Table 13-2 SPI Register Map and Reset Value
245
Table 14-1 TMR Functional Comparison
250
Figure 14-1 Basic Timer Block Diagram
251
Figure 14-2 Control Circuit with CK_INT Divided by 1
251
Figure 14-3 Counter Structure
252
Figure 14-4 Overflow Event When PRBEN=0
252
Figure 14-5 Overflow Event When PRBEN=1
252
Figure 14-6 Counter Timing Diagram with Internal Clock Divided by 4
252
Table 14-2 TMR6 and TMR7- Register Table and Reset Value
253
Figure 14-7 General-Purpose Timer Block Diagram
255
Figure 14-8 Count Clock
256
Figure 14-9 Use CK_INT to Drive Counter with Tmrx_Div=0X0 and Tmrx_Pr=0X16
256
Figure 14-10 Block Diagram of External Clock Mode a
257
Figure 14-11 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
257
Figure 14-12 Block Diagram of External Clock Mode B
258
Figure 14-13 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
258
Table 14-3 Tmrx Internal Trigger Connection
258
Figure 14-14 Counter Timing with Prescaler Value Changing from 1 to 4
259
Figure 14-15 Counter Structure
259
Figure 14-16 Overflow Event When PRBEN=0
260
Figure 14-17 Overflow Event When PRBEN=1
260
Figure 14-18 Counter Timing Diagram with Internal Clock Divided by 4
260
Figure 14-19 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
261
Figure 14-20 Encoder Mode Structure
261
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
262
Table 14-4 Counting Direction Versus Encoder Signals
262
Figure 14-22 Input/Output Channel 1 Main Circuit
263
Figure 14-23 Channel 1 Input Stage
263
Figure 14-24 Example of PWM Input Mode Configuration
264
Figure 14-25 PWM Input Mode
264
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
265
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
266
Figure 14-28 Upcounting Mode and PWM Mode a
266
Figure 14-29 Up/Down Counting Mode and PWM Mode a
266
Figure 14-30 One-Pulse Mode
267
Figure 14-31 Clearing Cxoraw (PWM Mode A) by EXT Input
267
Figure 14-32 Example of Reset Mode
268
Figure 14-33 Example of Suspend Mode
268
Figure 14-34 Example of Trigger Mode
268
Figure 14-35 Master/Slave Timer Connection
269
Figure 14-36 Using Master Timer to Start Slave Timer
269
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger
270
Table 14-5 Tmrx Register Map and Reset Value
270
Table 14-6 Standard Cxout Channel Output Control Bit
279
Figure 14-38 Block Diagram of General-Purpose TMR9/12
282
Figure 14-39 Block Diagram of General-Purpose TMR10/11/13/14
283
Figure 14-40 Count Clock
283
Figure 14-41 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
283
Figure 14-42 Block Diagram of External Clock Mode a
284
Figure 14-43 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
284
Figure 14-44 Counter Timing with Prescaler Value Changing from 1 to 4
285
Table 14-7 Tmrx Internal Trigger Connection
285
Figure 14-45 Counter Structure
286
Figure 14-46 Overflow Event When PRBEN=0
287
Figure 14-47 Overflow Event When PRBEN=1
287
Figure 14-48 Input/Output Channel 1 Main Circuit
288
Figure 14-49 Channel 1 Input Stage
288
Figure 14-50 Example of PWM Input Mode Configuration
289
Figure 14-51 PWM Input Mode
289
Figure 14-52 Capture/Compare Channel Output Stage (Channel 1)
290
Figure 14-53 C1ORAW Toggles When Counter Value Matches the C1DT Value
291
Figure 14-54 Upcounting Mode and PWM Mode a
291
Figure 14-55 One-Pulse Mode
291
Figure 14-56 Example of Reset Mode
292
Figure 14-57 Example of Suspend Mode
292
Figure 14-58 Example of Trigger Mode
293
Table 14-8 Tmrx Register Map and Reset Value
293
Table 14-9 Standard Cxout Channel Output Control Bit
298
Table 14-10 Tmrx Register Map and Reset Value
299
Table 14-11 Standard Cxout Channel Output Control Bit
303
Figure 14-59 Block Diagram of Advanced-Control Timer
304
Figure 14-60 Count Clock
305
Figure 14-61 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
305
Figure 14-62 Block Diagram of External Clock Mode a
306
Figure 14-63 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
306
Figure 14-64 Block Diagram of External Clock Mode B
307
Figure 14-65 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
307
Table 14-12 Tmrx Internal Trigger Connection
307
Figure 14-66 Counter Timing with Prescaler Value Changing from 1 to 4
308
Figure 14-67 Counter Structure
308
Figure 14-68 Overflow Event When PRBEN=0
309
Figure 14-69 Overflow Event When PRBEN=1
309
Figure 14-70 Counter Timing Diagram with Internal Clock Divided by 4
309
Figure 14-71 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
310
Figure 14-72 OVFIF in Upcounting Mode and Up/Down Counting Mode
310

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