Signal Block Diagram - Pioneer CDJ-2000NXS Service Manual

1

4.2 SIGNAL BLOCK DIAGRAM

A
SLOTIN MECHA ASSY
TRAVERSE MECHANISM
CD
SPINDLE OEIC
MOTOR
PICKUP ASSY
B
M M
C
LOADING
MOTOR
C
1
INSW
ASSY
M M
STEPPING
D
MOTOR SK
G
SDCB ASSY
CN5101
SD Card
Connector
E
JA6301
USB-A Jack
JA6302
USB-B Jack
H
USBB ASSY
F
12
1
2
POWER SUPPLY
T
ASSY
CN2
CN7302
LPS1
175
4 4
LPS2
5 5 176
6
D
SLMB
ASSY
1 1 13
B
SPCN
ASSY
E
MAIN ASSY
JA702
IC704
LAN
Ether PHY
Connector
CLK:25MHz
SDHC I/F (CLK: 27 MHz)
USB Full/High Speed I/F
IC701
USB-B IC 16
CLK:48MHz
2
3
POWER
A
SRVB ASSY
IC7002
FEP
15 19 29
111 109 112
IC7006
IC7004
SODC
128kB
8
FLASH
CLK:16.934MHz
119 120
62
46 5 4
IC7001
6ch
Servo Driver
CN7005
CN701
MII , MDC
Host I/F
MAIN System Bus
16 16 16
CS1
CS2
IC1 IC2 IC12
32MB 32MB 32MB
SDRAM SDRAM SDRAM SDRAM
Bus CLK Bus CLK Bus CLK
107.86MHz 107.86MHz 107.86MHz
CDJ-2000NXS
3
4
TFT-LCD MODULE
CN4013
IC4001
TFT CPU
CLK:24.576MHz
Core CLK:393.216MHz
CPU : MAIN->TFT
CLK: 6MHz
CPU : TFT->MAIN
CN4002
CN704
IC10
MAIN CPU
CLK:26.965MHz
Core CLK:323.58MHz
CS3
16
16 16
CS0
IC13
IC3
IC302
32MB
4MB
32MB
FLASH 16
SDRAM
Bus CLK
Bus CLK
107.86MHz
129.8304MHz
4
IC4018
Backlight
Power
16
32M
Bus C
16
16
2M
Se
CPU : MAIN->PANEL
CLK: 1MHz
IC1
Authent
I2C
IC
Control
Universa
Host-Port
Interface
U-HPI
BCLK
IC301
K3
DATA
DSP
T3
LRCLK
K4
CLK:16.9344MHz
Core CLK:389.4912MHz
S/PDIF
D8