VESTEL 17MB11 Service Manual
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VESTEL 17MB11 Service Manual

VESTEL 17MB11 Service Manual

50” plasma tv
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50" PLASMA TV
(17MB11)
SERVICE MANUAL

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  • Page 1 50” PLASMA TV (17MB11) SERVICE MANUAL...

  • Page 2: Table Of Contents

    TABLE OF CONTENTS INTRODUCTION ............................1 TUNER..............................1 IF PART (TDA9886) ..........................1 MULTI STANDARD SOUND PROCESSOR .................... 2 VIDEO SWITCH TEA6415 ........................2 AUDIO AMPLIFIER STAGE WITH TDA8928................... 2 POWER SUPPLY (SMPS) ........................3 MICROCONTROLLER ..........................3 SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A..............3 CLASS AB STEREO HEADPHONE DRIVER TDA1308 .................
  • Page 3 Pin Description ........................14 12.12.3. 12.13. 74LVC14A ............................15 Features ..........................15 12.13.1. Applications..........................15 12.13.2. Description..........................15 12.13.3. Pin Description ........................15 12.13.4. 12.14. LM1117............................15 General Description ....................... 15 12.14.1. Features ..........................15 12.14.2. Applications..........................16 12.14.3. Connection Diagrams ......................16 12.14.4.
  • Page 4 General Description ....................... 34 12.28.1. Features ..........................34 12.28.2. Pin Connections ........................34 12.28.3. 12.29. SDRAM 4M x 16 (MT48LC4M16A2TG-75)..................35 General Description ....................... 35 12.29.1. Features ..........................36 12.29.2. Pin Descriptions ........................36 12.29.3. 12.30. FLASH 8MBit........................... 37 Description..........................37 12.30.1.

  • Page 5: Introduction

    1. INTRODUCTION 50” Plasma TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1366*768 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L´ including German and NICAM stereo.

  • Page 6: Multi Standard Sound Processor

    I²C help, Audio amplifier and mute time constant, -bus transceivers and MAD (module address), Internal voltage stabilizer. 4. MULTI STANDARD SOUND PROCESSOR The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analogue TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analogue sound IF signal-in, down to processed analogue AF-out, is performed on a single chip.

  • Page 7: Power Supply (Smps)

    7. POWER SUPPLY (SMPS) The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer generates 145V for FBT input, +/-14V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V and 5V supplies for other different parts of the chassis.

  • Page 8: Ic Descriptions

    K3953M: Standard: • B/G • D/K • I • L/L’ Features TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz Constant group delay Suitable for CENELEC EN 55020 Terminals Tinned CuFe alloy Pin configuration 1 Input 2 Input - ground 3 Chip carrier - ground 4 Output...

  • Page 9: Mc34063

    12.1. MC34063 12.1.1. Description The MC34063A Series is a monolithic control circuit containing the primary functions required for DC– to–DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch.

  • Page 10: Pin Connections

    - Including 100 kHz (2.5V) and 400 kHz (5V) modes • Self-timed ERASE and WRITE cycles • Power on/off data protection circuitry • Endurance: - 10,000,000 Erase/Write cycles guaranteed for High Endurance Block - 1,000,000 E/W cycles guaranteed for Standard Endurance Block •...

  • Page 11: Pinning

    • Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response) • Gated phase detector for L/L accent standard • Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and positive modulated standards via I C-bus •...

  • Page 12: Features

    Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75Ω load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration.

  • Page 13: Pinning

    12.5.3. Pinning Mnemonic Function X7 (IPU) sense input from key matrix SSM (I) sense mode selection input Z0-Z3 (IPU) sense inputs from key matrix MDATA (OP3) generated output data modulated with 1/12 the oscillator frequency at a 25% duty factor DATA (OP3) generated output information 9-13...

  • Page 14: Pin Function Table

    12.6.3. Pin Function table Name Function A0, A1, A2 User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock Write Protect Input +4.5V to 5.5V Power Supply 12.6.4. Functional Descriptions The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver.

  • Page 15: Pin Connections And Short Descriptions

    12.7.3. Pin Connections and Short Descriptions SYMBOL TYPE DESCRIPTION Port 2: 8-bit programmable bidirectional port with alternative functions P2.0/PWM output for 14-bit high precision Pulse Width Modulator (PWM) P2.1/PWM0 outputs for 6-bit PWMs 0 to 6 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 Port 3: 8-bit programmable bidirectional port with alternative functions...

  • Page 16: Lm317

    crystal oscillator ground OSCGND 12 MHz crystal oscillator input XTALIN 12 MHz crystal oscillator output XTALOUT reset input; if this pin is HIGH for at least 2 machine cycles (24 RESET oscillator periods) while the oscillator is running, the device resets; this pin should be connected to via a capacitor periphery supply voltage (+3.3 V)

  • Page 17: Pin Connections

    • Pb-Free Packages are Available 12.9.3. Pin Connections 12.10. ST24LC21 12.10.1. Description The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This device can operate in two modes: Transmit Only mode and I C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK.

  • Page 18: Tlc7733

    12.11. TLC7733 12.11.1. Description The TLC77xx family of micropower supply voltage supervisors are designed for reset control, primarily in microcomputer and microprocessor systems. (. 2 V) is established, During power-on, RESET is asserted when V reaches 1 V. After minimum V the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage I(SENSE) remains below the threshold voltage.

  • Page 19: 74Lvc14A

    Ground (0V) 3-State output enable input (active LOW) Positive supply voltage 12.13. 74LVC14A 12.13.1. Features • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V •...

  • Page 20: Applications

    • Output Current 800mA • Line Regulation 0.2% (Max) • Load Regulation 0.4% (Max) • Temperature Range — LM1117 0°C to 125°C — LM1117I -40°C to 125°C 12.14.3. Applications • 2.85V Model for SCSI-2 Active Termination • Post Regulator for Switching DC/DC Converter •...

  • Page 21: Pin Description

    • DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package 12.15.3. Pin Description DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter Pin Name Description TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE, TxIN FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

  • Page 22: Pin Configurations

    • Low Temperature Coefficient 30 ppm /°C • Offered in TO-92, SOIC, SOT-89, SOT-23-5 • Improved Replacement in Performance for TL431 • Low Cost Solution 12.16.3. Pin Configurations 12.17. MSP34X0G (MSP3410G) Multistandard Sound Processor Family 12.17.1. Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards.

  • Page 23: Features

    Source Select S bus interface consists of five pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3.
  • Page 24 Connection Pin No. Pin Name Type Short Description (if not used) PLCC PSDIP PSDIP PQFP PLQFP 68-pin 64-pin 52-pin 80-pin 64-pin ADR_WS ADR word strobe Not connected ADR_DA ADR Data Output I2S_DA_IN1 S1 data input I2S_DA_OUT S data output I2S_WS IN/OUT S word strobe I2S_CL...

  • Page 25: Tda8928

    Not connected DACM_L Loudspeaker out, left DACM_R Loudspeaker out, right VREF2 Reference ground 2 DACA_L Headphone out, left DACA_R Headphone out, right Not connected Not connected RESETQ Power-on-reset Not connected Not connected Not connected I2S_DA_IN2 S2-data input DVSS Digital ground DVSS Digital ground DVSS...

  • Page 26: Tda1308

    12.19. TDA1308 12.19.1. General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

  • Page 27: Mst9883

    or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output of a character generator on a standard composite video background. 12.21. MST9883 12.21.1. General Description The MST9883C is a fully integrated analog interface for digitizing high-resolution RGB graphics signals from PC’s and workstations.

  • Page 28: Saa7118E

    12.22. SAA7118E 12.22.1. General Description The SAA7118E is a video capture device for applications at the image port of VGA controllers. Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video. The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation...

  • Page 29: Features

    12.22.2. Features Video acquisition/clock • Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals) • Up to eight analog Y + C inputs, split as desired •...

  • Page 30: Pinning

    Audio clock generation • Generation of a field-locked audio master clock to support a constant number of audio clocks per video field • Generation of an audio serial and left/right (channel) Digital I/O interfaces • Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification”...
  • Page 31 83H) TEST4 do not connect, reserved for future extensions and for testing: scan output TEST5 do not connect, reserved for future extensions and for testing TEST6 do not connect, reserved for future extensions and for testing VSSA4 ground for analog inputs AI4x AGND analog ground TEST7...
  • Page 32 digital ground 7 (peripheral cells) SSD7 IPD1 MSB - 6 of image port data output HPD7 MSB of host port data I/O, extended C R input for expansion port, extended C output for image port IPD0 LSB of image port data output AI2D differential input for ADC channel 2 (pins AI24 to AI21) AI23...
  • Page 33 (VSB) MSB − 6 of direct analog-to-digital converted output data ADP2 (VSB) digital supply voltage 11 (peripheral cells) DDD11 digital supply voltage 12 (core) DDD12 RTS0 real-time status or sync information, controlled by subaddresses 11H and 12H digital supply voltage 13 (peripheral cells) DDD13 AMXCLK audio master external clock input...

  • Page 34: Tps72501

    resistor is necessary (internal pull-down). 6. Pin RTCO operates as I 2 C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H. 7. Pin ALRCLK: 0 = 24.576 MHz crystal (default; Philips order number 4322 143 05291); 1 = 32.110 MHz crystal 12.23.

  • Page 35: Tsop1836

    12.24. TSOP1836 12.24.1. Description The TSOP18.. – series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier are assembled on lead frame, the epoxy package is designed as IR filter. Carrier frequency for TSOP1836 is 36kHz. The demodulated output signal can directly be decoded by a microprocessor. The main benefit is the reliable function even in disturbed ambient and the protection against uncontrolled output pulses.

  • Page 36: Pinning

    • Analog voltage range from • On-chip track and hold circuit • 8-bit successive approximation A/D conversion • Multiplying DAC with one analog output. 12.25.3. Pinning SYMBOL DESCRIPTION AINO analog inputs (A/D converter) AIN1 AIN2 AIN3 hardware address negative supply voltage C-bus data input/output C-bus clock input oscillator input/output...

  • Page 37: Applications

    12.26.3. Applications For use with Digital Displays • Flat-Panel (LCD, DLP) TVs • Rear Projection TVs • Plasma Displays • LCD Multimedia Monitors • Multimedia Projectors 12.27. PW181 12.27.1. General Description The PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display.

  • Page 38: Sil1169

    12.27.3. Applications • Multimedia Displays • Plasma Displays • Digital Television 12.28. SIL1169 12.28.1. General Description The SiI 1169 receiver uses PanelLink Digital technology to support high-resolution digital displays for PC and HDTV applications. The SiI 1169 device features High-bandwidth Digital Content Protection HDCP) for secure delivery of high-definition video, and comes with integrated, pre-programmed HDCP eys to simplify manufacturing and provide the highest level of security.

  • Page 39: Sdram 4M X 16 (Mt48Lc4M16A2Tg-75)

    12.29. SDRAM 4M x 16 (MT48LC4M16A2TG-75) 12.29.1. General Description The Micron ® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.

  • Page 40: Features

    12.29.2. Features • PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page •...

  • Page 41: Flash 8Mbit

    – Address input (A12) for the 256Mb and 512Mb devices 3, 9, 43, 49 Supply DQ Power: Isolated DQ power on the die for improved noise immunity. 6, 12, 46, 52 Supply DQ Ground: Isolated DQ ground on the die for improved noise immunity.

  • Page 42: Features

    compensation and a fixed-frequency oscillator. The LM2576 series offers a high efficiency replacement for popular three-terminal adjustable linear regulators. It substantially reduces the size of the heat sink, and in many cases no heat sink is required. A standard series of inductors available from several different manufacturers are ideal for use with the LM2576 series.

  • Page 43: Service Menu Settings

    13. SERVICE MENU SETTINGS All system, geometry and white balance alignments are performed in production service mode. Before starting the production mode alignments, make sure that all manual adjustments are done correctly. To start production mode alignments enter the MENU by pressing “M (MENU)” button and then press the digits 4, 7, 2 and 5 respectively.
  • Page 44 scart prescale By pressing button, select scart prescaler. Press button to set the scart prescaler. Scart prescale can be adjusted between 0 and 127. nicam prescale By pressing button, select nicam prescaler. Press button to set the nicam prescaler. Nicam prescale can be adjusted between 0 and 127.

  • Page 45: Calibration Menu

    13.2. calibration menu By pressing “◄/►” buttons select the second icon. calibration menu appears on the screen. calibration initial APS burn-in mode color temp 5500K 7500K 9300K user 6500K 6500K auto video format down to change cal. settings, scrolling menu initial APS By pressing button, select initial APS.

  • Page 46: Deinterlacer Menu

    color space Displays the current color space used. RGB, YPbPr SMPTE240, YPbPr REC709 and YCbCr REC601. test pattern By pressing button, select test pattern. Press button to set the test pattern. The options are: none, solid color and vert bars. color components By pressing button, select color components.
  • Page 47 dlti Digitial luma transition improvement: By pressing button, select dlti. DLTI can be adjusted between 0 and 255 by pressing button. luminance peaking By pressing button, select luminance peaking. Luminance peaking can be set to on or off by pressing button.

  • Page 48: Factory Settings Menu

    13.4. factory settings menu By pressing “◄/►” buttons select the fourth icon. Factory settings menu appears on the screen. factory settings brightness contrast sharpness color volume hp volume down to change factory settings Brightness, contrast, sharpness, color, volume and headphone volume factory settings can be seen in this menu.

  • Page 49: Block Diagram

    14. BLOCK DIAGRAM SC1_AUDIO_L/R_IN Saw Filter SC2_AUDIO_L/R_IN DDC_DATA_PC 8 Ohms Sound FAV_AUDIO_L/R_IN DDC_CLK_PC ST24LC21 TPA8928 QSS Main PC_AUDIO_L/R_IN DDC_V (E2PROM) (Class D Amp) PC_VS Sound 8 Ohms TUNER MAIN_AUDIO_L/R 9886 (Main) IC113 MSP 34XX HP_L/R Headphone TDA1308 Saw Filter LINE_L/R_OUT HP_L/R DDC_DATA_DVI (Headphone...

  • Page 50: Circuit Diagrams

    15. CIRCUIT DIAGRAMS Plasma TV Service Manual 25/08/2005...
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