Table of Contents
Advertisement
NOTE: The UH expects all uploaded blocks start with a well-formatted header. This header defines the
Destination where the binary data (red) inside the block should be copied. If no-copy (NC) flag (L) is set,
UH should skip copying the binary data. Size defines how many bytes of binary data there are. Jump
contains the address the UH should jump to (by means of a branch instruction) when it is done with the
block at hand. If no-jump (NJ) flag (LSB) is set, the UH shall skip the jump instruction.
2.1.3 Tasks Performed by the Driver
The driver parses the WRM file and uploads the firmware blocks based on the information to different WRM
block headers. The driver also runs in a loop implementing the following steps:
1. Copy SIZE bytes of opaque data to the "0x1ffe0000" location of SRAM.
2. Issue a READY interrupt to the wireless NIC.
3. Issue a RAM-Boot if the Boot-bit of the corresponding WRM block is set.
4. Wait for a READY interrupt from the wireless NIC.
5. Clear the READY interrupt when detected.
6. Timeout and fail the upload after MAX_WAIT microseconds.
After receiving READY interrupt for the last block in WRM file, the driver shall expect that the regular
firmware boot process has started, and it may continue with the regular PCI protocol initialization. Please
refer [1] for PCI protocol initialization procedure.
2.1.4 Overview of Firmware Upload
The firmware upload process entails the following:
1. The driver copies UH into device AHB-RAM memory.
2. The driver issue a RAM-Boot to boot the UH.
3. On booting UH installs itself at address 0 (ITCM) and starts communicating with the driver using PCI
interrupt (Software defined READY interrupt) as handshake signal to tell the other that they are ready for
the next block.
4. The driver copies next block in device memory and UH copies it from AHB-RAM to its destination address.
This step gets repeated till last WRM block gets transferred from host driver to device.
5. In last WRM block NJ bit is not set and code jumps to the Jump address. This is the address from where
firmware starts its execution.
6. The device informs driver its readiness by setting 'Initialized' bit in 'Host Interrupt' register.
2.1.4.1 RAMBoot
The device boots from Boot ROM by default. In this case, Boot ROM reads the Manufacturing ID, initializes
the CLK, device internal memory etc. After the firmware downloads, it gets initialized by issuing RAMBoot
from the Host. The Boot Process starts from the first instruction of the firmware.
The driver issues RAM-Boot using the following sequence of operations on the Control/Status register.
1. Clear the Reset bit.
2. Set the RAMBoot bit.
3. Set the Reset bit.
4. Clear the Reset bit.
2-3
SHoC Driver Design
Advertisement
Table of Contents
