Pioneer CDJ-1000MK3 Service Manual page 102

1
A
No. Pin Name
−
146 CAP1
147 Vss-PLL1 GND
148 Vss-PLL2 GND
149 CAP2 N.C.
150 Vcc-PLL2 V+1R8
151 AUDCK AUDCK
152 Vss GND
153 Vss GND
B
154 Vcc V+1R8
155 XTAL N.C.
156 EXTAL GND
157 STATUS0 TI PCMACK
158 STATUS1 TI BSACK
159 TCLK FPGA_XPRG
160 IREQOUT N.C.
161 VssQ GND
162 CKIO SH_66M
163 VccQ V+3R3
164 TxDO
CONFDAT/DASSO
C
CONFIG_CLK/DASCK
165 SCKO
166 TxD1 N.C.
167 SCK1 N.C.
168 TxD2 TXD2
169 SCK2 N.C.
170 RTS2 N.C.
−
171 RxDO
−
172 RxD1
173 Vss GND
174 RxD2 RxD2
D
175 Vcc V+1R8
176 CTS2 CTS2
177 MCS7 CONT0
178 MCS6 DMA RST
179 MCS5 CONT1
180 MCS4 CONT2
181 VssQ GND
182 WACKUP CARD RST
183 VccQ V+3R3
184 RESETOUT GSL RST
185 MCS3 MCS3
E
186 MCS2 CARD XINT
187 MCS1 ATAIRQ
188 MCS0 MCS0
189 DRAK0 N.C.
190 DRAK1 N.C.
191 DREQ0 XDREQ0
192 DREQ1 XDREQ1
193 RESETTP RSTCPU
194 CA CA
195 MD3 SHMD3
F
102
1
2
Signal Name I/O
−
External capacitor pin for PLL1
−
Ground for PLL1
−
Ground for PLL2
−
External capacitor pin for PLL2 (Not used)
−
Power supply for PLL2
−
For development
−
Ground
−
Ground
−
Power supply for core (1.8V)
−
Not used
−
Connect to ground
O TI DSP output data acknowledge
O
TI DSP input data acknowledge
O
PRG signal for FPGA configuration
−
Not used
−
Ground
I Clock input (65.975MHz)
−
Power supply for I/O (3.3V)
O
FPGA configuration/serial data output for DAC
O
FPGA configuration/serial clock output for DAC
−
Not used
−
Not used
O
TXD signal for production
−
Not used
−
Not used
−
Not used
−
Not used
−
Ground
I
RXD signal for production
−
Power supply for core (1.8V)
I Not used
O Control signal output
O FPGA reset output (reset with H)
I Control signal input
I Control signal input
−
Ground
O
TE4300 reset output (reset with H)
−
Power supply for I/O (3.3V)
O
ATA reset output (reset with H)
−
Not used
I TE4300 interrupt input
I FPGA interrupt input
−
Not used
−
Not used
−
Not used
I
DMA request 0 (FPGA)
−
Not used (connect to FPGA)
I Reset input
I Chip active (pull up with 3.3V)
I Clock mode setting (pull down)
2
3
Pin Function
CDJ-1000MK3
3
4
4