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texet TF-127 Service Manual

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SERVICE MANUAL
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  • Page 1 SERVICE MANUAL Premier confidential...
  • Page 2 Revision Table Revision Date REVISION HISTORY 2009/06/01 Initial revision Feature table Main Chip: AMLOGIC AML6210DP Internal: 128MB SDRAM + 2MB NOR FLASH/256Mb Nand FLASH Panel: 7" Analog TFT-LCD panels Interfaces: 4-in-1 card-reader (MS/SDHC/MMC/XD) USB 2.0 Host Port 6 buttons Head Phone Speaker 16Mb FLASH 12V I N...
  • Page 3 E. Card SD/MS_CLK XD_D3/SD_CLK C. Decoder SD/MS_CLK XD_D3/SD_CLK SD/MS_CMD XD_RB_RB M1_D[15..8] SD/MS_CMD XD_RB_RB M1_D[15..8] SD/MS_CLK XD_ALE_ALE XD_D2/SD_CMD VCOM SD/MS_CLK XD_ALE_ALE XD_D2/SD_CMD VCOM SD/MS_CMD XD_D6/SD_D2 XD_D3/SD_CLK SD/MS_CMD XD_D6/SD_D2 XD_D3/SD_CLK SD/MS_CMD XD_D2/SD_CMD XD_D4/SD_D0 SD/MS_CMD XD_D2/SD_CMD XD_D4/SD_D0 SD/MS_CLK XD_RE_RE XD_D5/SD_D1 SD/MS_CLK XD_RE_RE XD_D5/SD_D1 XD_D0 SD/MS/XD_IN XD_D6/SD_D2...
  • Page 4 12V Input &5V DC_IN DC_IN DC_IN FB21 CON6 EC113 FB25 C121 EC24 47uf/16V 0.1uF C120 10nf/NC 0.1uF FB26 220uf/16V +5VA GND_I +5VA dc_power LCD_5V LCD_5V LCD_3.3V LCD_3.3V DAC_3.3V C122 DAC_3.3V P+5V VCC1.2V 22UF/10V VCC1.2V 15uH/NC DC_IN DC_IN EC116 C119 0.1uF MP1411/NC C115 100uf/10V...
  • Page 5 LCD_5V BL_VCC FB17 BL_VCC LED_B+ CON11 L11 10uH SS14 EC159 C160 BHS3.5-2A C125 1uf/25v LED_GND 0.1uF 100uf/10V INV_GND INV_GND R180 BL_EN_IN INV_EN R184 R183 0.47 MP3202DJ 4.7K INV_GND INV_GND INV_GND L800 FB(50R) L801 FB(50R) INV_GND AGND BackLight Approved by: Title Size i s i Ver01...
  • Page 6 DAC_3.3V 1N4148 I2C_SCL I2C_SCL I2C_SDA I2C_SDA VBAT IRQ/FOUT ISL1208 0.1uF C108 32.768KHz GC5.5V 0.22F AGND Approved by: Title Size i s i Ver01 Checked by: I Rtc : e t 10 of 12...
  • Page 7 +5VA +5VA LCD_5V LCD_5V LCD_3.3V LCD_3.3V DAC_3.3V DAC_3.3V VCC1.2V VCC1.2V USB5V USB5V U311 VBUS1 VOUT FB20 VOUT R370 Core3.3V EC110 4.7k RT9701 100uf/10V 0.1uF R368 2.2K R373 MMBT3904 AGND AGND AGND AGND FB19 FB120 CON13 VBUS1 VBUS1 R117 R106 SHLD 0.1uF 0.1uF 100uf/10V...
  • Page 8 +5VA +5VA LCD_5V LCD_5V LCD_3.3V LCD_3.3V DAC_3.3V DAC_3.3V VCC1.2V VCC1.2V AUDIO_VCC AUDIO_VCC AUDIO_VCC AUDIO_VCC +5VA 100K R802 EC28 100K PH_ON J106 100uF/10V 0.1uF FB120 100K 3904 U113 AUDIO_VCC R803 4Q10 SPR_ SPR+ PGND ROUT+ ROUT- SE/BTL SPR+ R806 100K/NC C181 SPEAKER/NC PVDD HP/LINE...
  • Page 9 R173 22 NC V[14..1] CON8 VCOM RP24 VCOM 1.POL STVL STVD STVL 2.STVD OEV1 3.OEV R134 R135 +5VA CKV_P 4.CKV +5VA 3.3k LCD_5V STVU 5.STVU LCD_5V LCD_3.3V 6.GND1 LCD_3.3V 4x22 DAC_3.3V EDGSL LCD_10V 7.EDGSL DAC_3.3V C132 0.1uF LCD_3.3V VCC1.2V V[14..1] LCD_3.3V 8.VCC3.3 VCC1.2V...
  • Page 10 CARD PART +5VA +5VA LCD_5V LCD_5V LCD_3.3V LCD_3.3V DAC_3.3V DAC_3.3V VCC1.2V VCC1.2V DAC_3.3V RP10 RP11 4*4.7K 4*4.7K 4*4.7K CARD_VCC SD/MS/XD_IN XD_CD XD_RB XD_R/B XD_RE XD_RE XD_CE XD_CE XD_CLE XD_CLE XD_ALE XD_ALE RP12 XD_D2/SD_CMD XD_D2 SD_CMD MS_BS XD_D2/SD_CMD XD_WE XD_WE XD_D3/SD_CLK XD_D3 SD_CLK MS_CLK...
  • Page 11 Cancel 1X16 SDRAM MAK1 MAK2 M1_A[11..0] M1_A[11..0] M1_A0 M1_D0 M1_A1 M1_D1 M1_A2 M1_D2 M1_A3 M1_D3 AGND AGND M1_A4 M1_D4 M1_A5 M1_D5 M1_A6 M1_D6 M1_A7 M1_D7 M1_A8 M1_D8 M1_D[7..0] M1_D[7..0] M1_A9 M1_D9 M1_A10 M1_D10 DQ10 M1_D11 DQ11 M1_BA0 M1_D12 M1_BA0 DQ12 M1_D13 DQ13 M1_D7...
  • Page 12 Core3.3V DAC_3.3V RCR5102-293BSI Core3.3V RESET RESET_N RESET_N 2EC2 DAC_3.3V 22UF/1206 0.1UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 100uf/10V 100K/NC 0.01uF/NC EC13 AGND AGND Core1.2V Core3.3V AGND 100uf/10V 0.1uF CORE3.3V AGND AGND AGND NAND_R/B NAND_R/B R101 R102 NAND_nWE NAND_nWE 4.7K...
  • Page 13 K706ADV10 down left Core3.3V Core3.3V (10K) CON5 AGND 4 HEADER Core3.3V Remote_Control AGND REMOTE GND_2 3P-1.25 right 102/NC 0.1uF 0.01uF BAV70 BAV70 BAV70 ENTER AGND RETURN AGND AGND AGND Approved by: Title Size i s i Ver01 Checked by: KEY_IR_Usb.SCH : e t 12 of 12...
  • Page 24 DISPLAY CORPORATION LCD MODULE S P E C I F I C AT I O N Customer: Model Name: AT070TN82 SPEC NO.: A070-82-TT-01 Date: 2008/07/22 Version: ■ ■ ■ ■ Preliminary Specification □ □ □ □ Final Specification For Customer ’s Acceptance Approved by Comment Approved by...
  • Page 25 InnoLux copyright 2004 All rights reserved, Copying forbidden. Record of Revision Version Revise Date Page Content Pre-spec. 01 2008/07/22 Initial release. The copyright belongs to InnoLux. Any unauthorized use is prohibited.

  • Page 26: Table Of Contents

    Contents 1. General Specifications......................1 2. Pin Assignment........................2 2.1. TFT LCD Panel Driving Section..................2 2.2. Backlight Unit Section..................... 5 3. Operation Specifications ......................6 3.1. Absolute Maximum Ratings ..................... 6 3.2. Typical Operation Conditions ................... 7 3.2.1. Current Consumption ....................8 3.2.2.

  • Page 27: General Specifications

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 1/27 1. General Specifications Item Specification Remark LCD size 7.0 inch(Diagonal) Driver element a-Si TFT active matrix 800 × 3(RGB) × 480 Resolution Display mode Normally white, Transmissive 0.0635(W) × 0.1905(H) mm Dot pitch 152.4 (W) ×...

  • Page 28: Pin Assignment

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 2/27 2. Pin Assignment 2.1. TFT LCD Panel Driving Section FPC Connector is used for the module electronics interface. The recommended model is P-TWO “AF 730L-A2G1T” manufactured by P-TWO. Pin No. Symbol Function Remark Polarity selection...
  • Page 29 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 3/27 Gamma voltage level 8 Gamma voltage level 5 Gamma voltage level 3 Power Ground Red data(MSB) Red data Red data Red data Red data Red data(LSB) Power Ground Power Ground Green data(MSB) Green data Green data Green data...
  • Page 30 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 4/27 Blue data (MSB) Blue data Blue data Blue data Blue data Blue data (LSB) Right/ left selection Note 1,2 Gamma voltage level 1 Gamma voltage level 4 Gamma voltage level 7 Gamma voltage level 10 Gamma voltage level 12 Gamma voltage level 13...

  • Page 31: Backlight Unit Section

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 5/27 Note 2: Definition of scanning direction. Refer to the figure as below: Left Right Active area Down Note 3: When REV=”L”, it’s under normal operation. When REV=”H”, these data will be inverted. 2.2.

  • Page 32: Operation Specifications

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 6/27 3. Operation Specifications 3.1. Absolute Maximum Ratings (Note 2) Values Item Symbol Unit Remark Min. Max. -0.5 -0.5 13.5 Power voltage -0.3 20.0 -13.0 33.0 V1~V7 0.4 AV +0.3 Note 1 Input signal voltage V8~V14 -0.3...

  • Page 33: Typical Operation Conditions

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 7/27 3.2. Typical Operation Conditions (Note 1) Values Item Symbol Unit Remark Min. Typ. Max. Note 2 10.2 10.4 10.6 Power voltage 15.3 16.0 16.7 -7.7 -7.0 -6.3 (V1+V14)/2 =5.2V Input signal voltage V1~V7 0.4 AV -0.1...

  • Page 34: Current Consumption

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 8/27 3.2.1. Current Consumption Values Symbol Unit Remark Item Min. Typ. Max. =16.0V = -7.0V Current for Driver 10.0 =3.3V 40.0 50.0 =10.4V 3.2.2. Backlight Driving Conditions Values Symbol Unit Remark Item Min.

  • Page 35: Power Sequence

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 9/27 3.3. Power Sequence 1. Power on: → → → → VGL→ → → → VGH→ → → → Data→ → → → B/L 2. Power off: B/L→ → → → Data→ → → → VGH→ → → → VGL→ → → → DV Note: Data include DCLK,POL,OEV,CKV,STVU,STVD,STHL,STHR,LD,R0~R5,G0~G5,B0~B5 The copyright belongs to InnoLux.

  • Page 36: Timing Characteristics

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 10/27 3.4. Timing Characteristics 3.4.1. Timing Conditions Values Item Symbol Unit Remark Min. Typ. Max. DCLK frequency Fdclk DCLK cycle Tcph DCLK pulse width Data set-up time Data hold time Time that the last data to LD Tcph Pulse width of LD Twld...
  • Page 37 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 11/27 Output rise time Ttlh 1000 Output falling time Tthl OEV pulse width Twcl OEV to Driver output delay time Horizontal lines per field Vertical display timing range The copyright belongs to InnoLux. Any unauthorized use is prohibited.

  • Page 38: Timing Diagram

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 12/27 3.4.2. Timing Diagram The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 39 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 13/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 40 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 14/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 41 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 15/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 42 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 16/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 43 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 17/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 44 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 18/27 The copyright belongs to InnoLux. Any unauthorized use is prohibited.

  • Page 45: Optical Specifications

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 19/27 4. Optical Specifications Values Item Symbol Condition Unit Remark Min. Typ. Max. θ Φ=180°(9 o’clock) θ Φ=0°(3 o’clock) Viewing angle Note 1 degree (CR≥ 10) θ Φ=90°(12 o’clock) θ Φ=270°(6 o’clock) msec Note 3 Response time...
  • Page 46 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 20/27 Note 1: Definition of viewing angle range Normal line θ=Φ=0° Φ=90° 12 o’clock direction θ θ θ θ Φ=180° Φ=0° Active Area Φ=270° 6 o’clock direction Fig. 4-1 Definition of viewing angle Note 2: Definition of optical measurement system.
  • Page 47 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 21/27 Note 3: Definition of Response time The response time is defined as the LCD optical switching time interval between “White” state and “Black” state. Rise time (T ) is the time between photo detector output intensity changed from 90% to 10%.
  • Page 48 SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 22/27 Note 7: Definition of Luminance Uniformity Active area is divided into 9 measuring areas (Refer to Fig. 4-4 ).Every measuring point is placed at the center of each measuring area. Luminance Uniformity (Yu) L-------Active area length...

  • Page 49: Reliability Test Items

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 23/27 5. Reliability Test Items (Note3) Item Test Conditions Remark Ta = 85℃ 240 hrs High Temperature Storage Note 1,Note 4 Low Temperature Storage Ta = -30℃ 240hrs Note 1,Note 4 Ts = 85℃ 240hrs High Temperature Operation Note 2,Note 4...

  • Page 50: General Precautions

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 24/27 6. General Precautions 6.1. Safety Liquid crystal is poisonous. Do not put it in your mouth. If liquid crystal touches your skin or clothes, wash it off immediately by using soap and water. 6.2.

  • Page 51: Mechanical Drawing

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 25/27 7. Mechanical Drawing The copyright belongs to InnoLux. Any unauthorized use is prohibited.

  • Page 52: Package Drawing

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 26/27 8. Package Drawing 8.1. Packaging Material Table Unit Model Item Dimensions(mm) Weight Quantity Remark (Material) (kg) AT070TN82 50pcs × × Module BC Corrugated 512 × 349 × 226 Partition 1.466 1 set Paper Corrugated BC Corrugated...

  • Page 53: Packaging Drawing

    SPEC NO.: A070-82-TT- 01 Date : 2008/07/22 Page: 27/27 8.3. Packaging Drawing The copyright belongs to InnoLux. Any unauthorized use is prohibited.
  • Page 54 AML6210DP A/V Processor User Guide Version 0.2 AML 6210DP A/V Processor User’s Guide AMLOGIC, Inc. 3930 Freedom Circle Santa Clara, CA 95054 U.S.A. www.amlogic.com AMLOGIC reserves the right to change any information described herein at any time without notice. AMLOGIC assumes no responsibility or liability from use of such information. 5/19/2008 1/24 AMLOGIC Proprietary...
  • Page 55 AML6210DP A/V Processor User Guide Version 0.2 Table of Contents INTRODUCTION..............................4 FEATURES................................5 EXTERNAL INTERFACES..........................7 ..........................7 LOBAL ONFIGURATIONS 3.1.1 Power-On Configuration..........................7 3.1.2 Clocks................................9 3.1.3 JTAG for Software Development ........................9 3.1.4 GPIOs................................10 ............................. 11 EMORY NTERFACES 3.2.1 SDRAM Interfaces ............................
  • Page 56 AML6210DP A/V Processor User Guide Version 0.2 Revision History Revision Revised Changes Number Date 2008/3/3 bwester Initial release 2008/3/3 Bwester Fix some errors in diagram and text 5/19/2008 3/24 AMLOGIC Proprietary...

  • Page 57: Introduction

    AML6210DP A/V Processor User Guide Version 0.2 1 Introduction The AML6210DP A/V processor is a complete integrated system targeting the digital picture frame market. The device combines a super fast JPEG decoder, all digital LCD drivers/TCON signals, USB and card-reader I/Os and a 32-bit host CPU in a small 144 pin package.

  • Page 58: Features

    AML6210DP A/V Processor User Guide Version 0.2 2 Features The AML6210DP chip is very flexible and most of the capabilities are under firmware control. The following list of features may or may not be included in the firmware library or binary, depending on the actual application and platform.
  • Page 59 AML6210DP A/V Processor User Guide Version 0.2 DMA support for data movement for BULK, INTR and ISO transfer USB device driver, native USB protocol stack supported in AVOS firmware Integrated support for Mass-storage class (MS-Class) and Picture Transfer Protocol (PTP) USB Hub support Audio and image decoding from USB attached MS-Class or PTP devices Connecting to PCs or Apple computers as USB MS-Class devices...

  • Page 60: External Interfaces

    AML6210DP A/V Processor User Guide Version 0.2 3 External Interfaces 3.1 Global Configurations 3.1.1 Power-On Configuration The chip has a common active-low reset signal called reset_n. This signal puts the entire chip into a known state by resetting internal registers and state-machines to their default states. Typically this signal is held low for at least 100 msec after the power and crystal clock is stabilized.
  • Page 61 AML6210DP A/V Processor User Guide Version 0.2 m1_a_10 m1_we_n m1_dqm1 Power reset_n Applied Powe-On Configuration M1_* Logic FLASH Controller SDRAM SDRAM (1Mx16) Controller 8-bit Flash 5/19/2008 8/24 AMLOGIC Proprietary...

  • Page 62: Clocks

    AML6210DP A/V Processor User Guide Version 0.2 3.1.2 Clocks The AML6210DP has multiple internal clock domains, but all the internal clock domains are derived from a single external reference: OSC. As illustrated below, the crystal/oscillator pin pairs (OSCIN/OSCOUT) can be connected to a crystal or driven from an external oscillator. In the typical A/V application, a 27 MHz crystal is connected to the OSC pins.

  • Page 63: Gpios

    AML6210DP A/V Processor User Guide Version 0.2 3.1.4 GPIOs Configurable hardware controllers (e.g. i2c, card-reader, etc.) and DMAs are integrated into the AML6210DP device to speed up the common operations and relieve the core RISC for user-level applications. Since hardware controllers and state-machines cannot cover all possible external devices or system-level signals, numerous general-purpose I/O pins are available on the chip for purpose like Portable Media Player keypads.

  • Page 64: Memory Interfaces

    AML6210DP A/V Processor User Guide Version 0.2 3.2 Memory Interfaces 3.2.1 SDRAM Interfaces The AML6210DP device uses external SDRAM for data storage and code execution. The SDRAM1 interface is labeled as m1_* interface. The SDRAM interface can access up to 16M bytes of memory. Depending on the application, 166MHz 4Mx16 or 8Mx16 SDRAM chips can be used.
  • Page 65 AML6210DP A/V Processor User Guide Version 0.2 very large capacity that ranges from 32MB to more than 1GB. The NAND FLASH should be connected as indicated in the following diagram: R/B* NAND_R/nB NAND_nRE NAND_CE NAND_nWE M1_BA1/NAND_CLE M1_BA0/NAND_ALE DQ[7:0] M1_D[7:0] 8-bit NAND FLASH 5/19/2008 12/24 AMLOGIC Proprietary...

  • Page 66: Audio Interfaces

    AML6210DP A/V Processor User Guide Version 0.2 3.3 Audio Interfaces A pair of audio DACs is provided in the AML6210DP device. The audio DACs are designed for connecting to small speaker inside the photo frame or ear buds for external listening. A simple external amplifier is needed. Please see the following sample circuit diagram.

  • Page 67: Display Output Interfaces

    AML6210DP A/V Processor User Guide Version 0.2 3.4 Display Output Interfaces 3.4.1 Digital Output The AML6210DP integrated internal LCD video scalar and encoder and high-resolution triple panel DACs (PDAC) for direct connection to digital LCD panels. The LCD scale and encoder convert the images to the LCD resolution and prepare the image to be displayed.

  • Page 68: Peripherals

    AML6210DP A/V Processor User Guide Version 0.2 3.5 Peripherals 3.5.1 Card-Reader Interface The AML6210DP have an integrated hardware controller for SD/MS/MMC/xD card-reader operations. The hardware controller is capable of executing the low-level card interface protocols, computing the CRC or checksum, and transferring data to/from SDRAM. The hardware provides interface for the necessary signals (e.g.

  • Page 69: Operating Conditions

    AML6210DP A/V Processor User Guide Version 0.2 4 Operating Conditions 4.1 DC Characteristics Table 4-1 DC Characteristics = 3.3 +/- 0.3V, T = 0 to 65°C Symbol Parameters Condition Unit High Level Input Low Level Input -0.3 Schmitt trigger, positive going Threshold Schmitt trigger, negative going threshold 0.93 High-level output voltage...

  • Page 70: Pin-Out

    AML6210DP A/V Processor User Guide Version 0.2 5 Pin-out The AML6210DP A/V processor pin-out is described in the following table. Abbreviations: I == Input digital pin, O == Output digital pin, I/O == Input/Output pin AI == Analog input pin, AO == Analog output pin, AIO == Analog input/output pin P == Power pin, AP == Analog power pin, NC == No connection Pin # Pin Name...
  • Page 71 AML6210DP A/V Processor User Guide Version 0.2 Pin name Description Comments / Alternate usage Type M1_A_11 M1_A_11 SDRAM1 and/or FLASH M1_BA1 M1_BA1 SDRAM1 and/or FLASH M1_BA0 M1_BA0 SDRAM1 and/or FLASH VDD33 I/O Power 3.3V Digital I/O power 3.3V M1_CLKO M1_CLKO SDRAM1 and/or FLASH M1_DQM1 M1_DQM1...
  • Page 72 AML6210DP A/V Processor User Guide Version 0.2 Pin name Description Comments / Alternate usage Type USB Mini-receptacle Identifier between mini- USBA_id USBA identifier A/mini-B plug USB power supply pin (5 volt). An off-chip charge pump is used to provide power to the USBA_vbus USBA mini VBUS VBUS pin.
  • Page 73 AML6210DP A/V Processor User Guide Version 0.2 GPIO GPIO General Purpose I/O or CARD_ENABLE XD_D0 Card Reader I/O Card Reader I/F or GPIO XD_D1 Card Reader I/O Card Reader I/F or GPIO XD_D2 // SD_CMD Card Reader I/O Card Reader I/F or GPIO XD_D3 // SD_CLK Card Reader I/O Card Reader I/F or GPIO...

  • Page 74: Package Pin-Out Diagram

    AML6210DP A/V Processor User Guide Version 0.2 5.1 Package pin-out diagram 108 VDD33 VAA3V 107 XD_WP APAD0 106 XD_RB APAD1 105 XD_CLE AGND 104 XD_ALE TCON_STH2 103 XD_CE TCON_STH1 102 XD_READY TCON_OEV1 101 XD_WE TCON_CPV1 100 XD_RE VDD33 TCON_STV1 10 99 VSS TCON_STV2 11 98 I2C_DATA...

  • Page 75: Jtag Interface Multi-Function Pins

    AML6210DP A/V Processor User Guide Version 0.2 PIN# PACKAGE PIN NAME GPIO XD_RE XD_RE AT_GPIO0 XD_WE XD_WE AT_GPI XD_READY XD_READ AT_GPIO2 XD_CE XD_CE AT_GPIO3 XD_ALE XD_ALE AT_GPIO6 XD_CLE AT_GPIO7 XD_D0 XD_D0 AT_GPIO8 XD_D1 XD_D1 AT_GPIO9 XD_D2 XD_D2 SD_CMD _STB AT_GPIO10 XD_D3 XD_D3 SD_CLK...
  • Page 76 AML6210DP A/V Processor User Guide Version 0.2 M1_A_2 _A_2 FLASH_A_2 M1_A_1 M1_A_1 FLASH_A_1 M1_A_0 M1_A_0 FLASH_A_0 M1_A_4 M1_A_4 FLASH_A_4 M1_A_5 M1_A_5 FLASH_A_5 M1_A_6 M1_A_6 FLASH_A_6 M1_A_7 M1_A_7 FLASH_A_7 M1_A_8 M1_A_8 FLASH_A_8 M1_A_9 M1_A_9 FLASH_A_9 M1_A_10 M1_A_10 FLASH_A_10 M1_A_11 M1_A_11 FLASH_A_11 M1_BA1 M1_BA1 M1_BA0...

  • Page 77: Mechanical Specifications

    AML6210DP A/V Processor User Guide Version 0.2 6 Mechanical Specifications The AML6210DP A/V processor is packaged using a 144 pins LQFP package. The mechanical dimensions are given in millimeters as below: 5/19/2008 24/24 AMLOGIC Proprietary...
  • Page 78 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 2Gb NAND FLASH HY27UF(08/16)2G2B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Jan.
  • Page 79 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Document Title 2Gbit (256Mx8bit) NAND Flash Memory Revision History Revision No. History Draft Date Remark Jul. 03. 2007 Preliminary Initial Draft. 1) Add ULGA Package. - Figures & texts are added. Sep. 11. 2007 Preliminary 2) Change tRCBSY to tRBSY 3) Change figure 13...
  • Page 80 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES STATUS REGISTER - Cost effective solutions for mass storage applications - Normal Status Register (Read/Program/Erase) - Extended Status Register (EDC) MULTIPLANE ARCHITECTURE - Array is split into two independent planes. Parallel ELECTRONIC SIGNATURE Operations on both planes are available, halving - 1st cycle : Manufacturer Code...
  • Page 81 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 1.SUMMARY DESCRIPTION Hynix NAND HY27UF(08/16)2G2B Series have 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
  • Page 82 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure1: Logic Diagram IO15 - IO8 Data Input / Outputs (x16 only) IO7 - IO0 Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection...
  • Page 83 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 2: 48TSOP1 Contact, x8 and x16 Device Figure 3: 63FBGA Contactions, x8 Device (Top view through package) Rev 0.2 / Jan. 2008...
  • Page 84 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 4. 52-ULGA Contactions, x8 Device (Top view through package) Rev 0.2 / Jan. 2008...
  • Page 85 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 1.2 PIN DESCRIPTION Pin Name Description DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to IO8-IO15 High-Z when the device is deselected or the outputs are disabled.
  • Page 86 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle Table 3: Address Cycle Map(x8) NOTE: 1. L must be set to Low. I/O8- IO15 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle Table 4: Address Cycle Map(x16) NOTE: 1.
  • Page 87 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash MODE Rising Command Input Read Mode Rising Address Input(5 cycles) Rising Command Input Write Mode Rising Address Input(5 cycles) Rising Data Input Falling Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect 0V/Vcc...
  • Page 88 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 2. BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
  • Page 89 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3. DEVICE OPERATION 3.1 Page Read This operation is operated by writing 00h and 30h to the command register along with five address cycles. Two types of operations are available: random read, serial page read. The random read mode is enabled when the page address is changed.
  • Page 90 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.3 Multi Plane Program Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane. A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
  • Page 91 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.6 Copy-back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved.
  • Page 92 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.8 EDC Operation Error Detection Code check automatically starts immediately after device becomes busy for a copy back program oper- ation (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 bytes, where each 528byte group is composed by 512 bytes of main array and 16 bytes of spare area (see Table 20,21).
  • Page 93 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.13 Cache Read Cache read operation allows automatic download of consecutive pages. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will be uninterrupted.
  • Page 94 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 4. OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides hardware pro- tection and is recommended to be kept at VIL during power-up and power-down.
  • Page 95 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Parameter Symbol Unit Valid Block 2008 2048 Blocks Number Table 7 : Valid Blocks Numbers NOTE: 1. The 1st block is guaranteed to be a valid block at the time of shipment. Symbol Parameter Value Unit Ambient Operating Temperature (Commercial Temperature Range)
  • Page 96 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 5: Block Diagram Rev 0.2 / Jan. 2008...
  • Page 97 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.3Volt Parameter Symbol Test Conditions Unit Sequential =25ns Read CE=V =0mA Operating Current Program Erase CE=V Stand-by Current (TTL) WP=0V/Vcc CE=Vcc-0.2, Stand-by Current (CMOS) WP=0V/Vcc Input Leakage Current 0 to Vcc (max) ± 10 Output Leakage Current =0 to Vcc (max) ±...
  • Page 98 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Item Symbol Test Condition Unit Input / Output Capacitance Input Capacitance Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Symbol Unit Program Time / Multi-Plane Program Time PROG Dummy Busy Time for Two Plane Program DBSY Number of partial Program Cycles in the same page Cycles...
  • Page 99 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.3V Parameter Symbol Unit CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to register ALE to RE Delay...
  • Page 100 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Page Program Block Erase Read Cache Read CODING Pass / Fail Pass / Fail Pass: ‘0’ Fail: ‘1’ Ready / P/E/R Ready / Busy Ready / Busy Active: ‘0’ Idle:’1’ Busy Controller Bit Ready / Ready / Busy Ready / Busy Ready/Busy...
  • Page 101 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Description IO5 IO4 IO3 IO2 IO1 IO0 Die / Package 2 Level Cell 4 Level Cell Cell Type 8 Level Cell 16 Level Cell Number of Simultaneously Programmed Pages Interleave program Between multiple chips Supported Write Cache Supported...
  • Page 102 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Description IO6 IO5 IO4 IO3 IO2 Plane Number 64Mb 128Mb 256Mb 512Mb Plane Size (w/o redundant Area) Reserved Table 19: 5rd Byte of Device Idendifier Description Rev 0.2 / Jan. 2008...
  • Page 103 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Table 20: Page organization in EDC units (x8) Table 21: Page organization in EDC units (x16) Copy back Program CODING Pass/Fail Pass: ‘0’ Fail: ‘1’ EDC status NO error: ‘0’ EDC Validity Invalid: ‘0’ Valid: ‘1’ Ready/Busy Busy: ‘0’...
  • Page 104 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 6: Command Latch Cycle Figure 7: Address Latch Cycle Rev 0.2 / Jan. 2008...
  • Page 105 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 8: Input Data Latch Cycle Rev 0.2 / Jan. 2008...
  • Page 106 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 10: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev 0.2 / Jan. 2008...
  • Page 107 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 11: Status Read Cycle Figure 12: Read1 Operation (Read One Page) Rev 0.2 / Jan. 2008...
  • Page 108 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 13: Read1 Operation intercepted by CE Rev 0.2 / Jan. 2008...
  • Page 109 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 14 : Random Data output Rev 0.2 / Jan. 2008...
  • Page 110 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 15: Read Operation with Read Cache Rev 0.2 / Jan. 2008...
  • Page 111 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 16: Page Program Operation Rev 0.2 / Jan. 2008...
  • Page 112 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 17: Random Data In Rev 0.2 / Jan. 2008...
  • Page 113 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 18: Copy Back Program Operation Rev 0.2 / Jan. 2008...
  • Page 114 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 19: Copy Back Program Operation with Random Data Input Rev 0.2 / Jan. 2008...
  • Page 115 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 20: Block Erase Operation (Erase One Block) Rev 0.2 / Jan. 2008...
  • Page 116 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 21: Multiple plane page program Rev 0.2 / Jan. 2008...
  • Page 117 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 22: Multiple plane erase operation Rev 0.2 / Jan. 2008...
  • Page 118 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 23: Multi plane copyback program Operation Rev 0.2 / Jan. 2008...
  • Page 119 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 24: Read ID Operation Rev 0.2 / Jan. 2008...
  • Page 120 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash System Interface Using CE don’t care To simplify system interface, CE signal is ignored during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
  • Page 121 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 27: Reset Operation Figure 28: Power On and Data Protection Timing VTH = 2.5 Volt for 3.3 Volt Supply devices Rev 0.2 / Jan. 2008...
  • Page 122 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 29: Ready/Busy Pin electrical specifications Rev 0.2 / Jan. 2008...
  • Page 123 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 30: page programming within a block Rev 0.2 / Jan. 2008...
  • Page 124 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor.
  • Page 125 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Bad Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register.
  • Page 126 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 33~36) Figure 33: Enable Programming Figure 34: Disable Programming Rev 0.2 / Jan.
  • Page 127 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 35: Enable Erasing Figure 36: Disable Erasing Rev 0.2 / Jan. 2008...
  • Page 128 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 37: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline millimeters Symbol 1.200 0.050 0.150 0.980 1.030 0.170 0.250 0.100 0.200 0.100 11.910 12.000 12.120 19.900 20.000 20.100 18.300 18.400 18.500 0.500 0.500...
  • Page 129 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 38: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline NOTE: Drawing is not to scale. Millimeters Symbol 0.80 0.90 1.00 0.25 0.30 0.35 0.55 0.60 0.65 0.40 0.45 0.50 8.90 9.00 9.10...
  • Page 130 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Figure 39: 52-ULGA, 12 x 17mm, Package Outline (Top view through package) millimeters Symbol 16.90 17.00 17.10 13.00 12.00 11.90 12.00 12.10 10.00 6.00 1.00 1.50 2.00 1.00 1.00 0.65 0.65 0.70 0.75 0.95 1.00 1.05 Table 26: 52-ULGA, 12 x 17mm, Package Mechanical Data...
  • Page 131 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash MARKING INFORMATION - TSOP1 / FBGA / ULGA P a ck a g M a rk in g E x a m p le T S O P 1 F B G A U L G A - h y n ix : H yn ix S ym bo l - K O R...

  • Page 132: Ordering Information

    ISL1208 ® ® Real Time Clock/Calendar Data Sheet July 29, 2005 FN8085.3 Low Power RTC with Battery Backed Features SRAM • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds The ISL1208 device is a low power real time clock with - Day of the Week, Day, Month, and Year timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup...
  • Page 133 ISL1208 Block Diagram Seconds BUFFER INTERFACE Minutes CONTROL BUFFER LOGIC Hours Day of Week CRYSTAL Date OSCILLATOR DIVIDER Month Year FREQUENCY ALARM CONTROL REGISTERS TRIP USER SWITCH SRAM IRQ/ INTERNAL SUPPLY Pin Descriptions NUMBER SYMBOL DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal.
  • Page 134 ISL1208 Absolute Maximum Ratings Voltage on V , SCL, SDA, and IRQ pins Storage Temperature ......-65°C to +150°C (respect to ground) .
  • Page 135 ISL1208 Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS (Note 4) UNITS NOTES Cpin SDA and SCL pin capacitance = 25°C, f = 1MHz, V = 5V, = 0V, V = 0V SCL frequency Pulse width suppression time at SDA Any pulse narrower than the max spec...
  • Page 136 ISL1208 SDA vs SCL Timing HIGH SU:DAT SU:STA HD:DAT SU:STO HD:STA (INPUT TIMING) (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change Will change from LOW from LOW to HIGH to HIGH May change Will change from HIGH from HIGH...
  • Page 137 ISL1208 Typical Performance Curves Temperature is 25°C unless otherwise specified 1E-6 1E-6 900E-9 800E-9 800E-9 700E-9 600E-9 600E-9 500E-9 400E-9 400E-9 300E-9 200E-9 200E-9 100E-9 000E+0 000E+0 TEMPERATURE (°C) FIGURE 1. I vs V FIGURE 2. I vs TEMPERATURE AT V = 3V 2.4E-6 2.4E-06...
  • Page 138 ISL1208 EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V = 5V 5.0V FOR V = 0.4V 1533Ω AND I = 3mA IRQ/FOUT FIGURE 8. RECOMMENDED CRYSTAL CONNECTION 100pF This input provides a backup supply voltage to the device. FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE supplies power to the device in the event that the V DEVICE WITH V = 5.0V...
  • Page 139 ISL1208 the ISL1208 for up to 10 years. Another option is to use a The I C bus is deactivated in battery backup mode to provide Super Cap for applications where V is interrupted for up lower power. Aside from this, all RTC functions are to a month.
  • Page 140 ISL1208 not begin incrementing until at least one byte is written to the C Serial Interface clock register. The ISL1208 has an I C serial bus interface that provides access to the control and status registers and the user Accuracy of the Real Time Clock SRAM.
  • Page 141 ISL1208 Write capability is allowable into the RTC registers (00h to instruction latches all clock registers into a buffer, so an 06h) only when the WRTC bit (bit 4 of address 07h) is set to update of the clock does not change the time being read. A “1”.
  • Page 142 ISL1208 Real Time Clock Registers REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a “1” after a total power failure. This is a read Addresses [00h to 06h] only bit that is set by hardware (ISL1208 internally) when the RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) device powers up after having lost all power to the device.
  • Page 143 ISL1208 FREQUENCY OUT CONTROL BITS (FO <3:0>) is cleared to “0”, the alarm function is disabled. The alarm function can operate in either a single event alarm or a periodic These bits enable/disable the frequency output function and interrupt alarm (see IM bit). select the output frequency at the IRQ/F pin.
  • Page 144 ISL1208 and X2 pins to ground (see Figure 11). The value of C TABLE 5. DIGITAL TRIMMING REGISTERS is given by the following formula: DTR REGISTER ESTIMATED FREQUENCY ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 16 b5 8 b4 4 b3 2 b2 1 b1 0.5 b0...
  • Page 145 ISL1208 Below are examples of both Single Event and periodic Once the registers are set, the following waveform will be Interrupt Mode alarms. seen at IRQ-: Example 1 – Alarm set with single interrupt (IM=”0”) RTC and alarm registers are both “30” sec A single alarm will occur on January 1 at 11:30am.
  • Page 146 ISL1208 receiver pulls the SDA line LOW to acknowledge the Byte of a write operation. The master must respond with an reception of the eight bits of data (See Figure 13). ACK after receiving a Data Byte of a read operation. The ISL1208 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte.
  • Page 147 ISL1208 Device Addressing Write Operation Following a start condition, the master must output a Slave A Write operation requires a START condition, followed by a Address Byte. The 7 MSBs are the device identifier. These valid Identification Byte, a valid Address Byte, a Data Byte, bits are “1101111”.
  • Page 148 ISL1208 Application Section In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature Oscillator Crystal Requirements is available for the ISL1208. There are 3 bits known as the The ISL1208 uses a standard 32.768kHz crystal. Either Digital Trimming Register (DTR).
  • Page 149 ISL1208 A system to implement temperature compensation would Do not run the serial bus lines or any high speed logic lines consist of the ISL1208, a temperature sensor, and a in the vicinity of the crystal. These logic level lines can microcontroller.
  • Page 150 ISL1208 part in these equations, and a typical value was chosen for Combining with Equation 2 gives the equation for backup example purposes. For a robust design, a margin of 30% time: should be included to cover supply current and capacitance * (V ) / (I BACKUP...
  • Page 151 ISL1208 Packaging Information 8-Lead Miniature Small Outline Gull Wing Package Type M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 0.0256 (0.65) Typ. (0.30 + 0.15 / -0.05) R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 7°...
  • Page 152 ISL1208 Packaging information 8-Lead Plastic, SOIC, Package Code S8 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.050 (1.27) 0.010 (0.25) 0.010 (0.25) 0.050"Typical...
  • Page 153 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM 128Mb F-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) Revision 1.2 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.2 August 2004...
  • Page 154 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Revision History Revision 1.0 (January, 2004) - First release. Revision 1.1 (May, 2004) • Added Note 5. sentense of tRDL parameter. Revision 1.2 (August, 2004) • Corrected typo. Rev. 1.2 August 2004...
  • Page 155 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address •...
  • Page 156 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Package Physical Dimension 0~8°C 0.25 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 22.62 0.891 22.22 ± 0.10 0.21 ± 0.05 1.00 ± 0.10 1.20 ± 0.004 ± 0.002 0.875 ± 0.004 0.008 0.039 0.047 0.10...
  • Page 157 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM FUNCTIONAL BLOCK DIAGRAM Data Input Register LDQM Bank Select 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Column Decoder Latency &...
  • Page 158 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM PIN CONFIGURATION (Top view) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 LDQM N.C/RFU N.C/RFU N.C/RFU UDQM A10/AP A10/AP A10/AP 54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Name Input Function System clock Active on the positive going edge to sample all inputs.
  • Page 159 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss -1.0 ~ 4.6 Voltage on V supply relative to Vss -1.0 ~ 4.6 °C Storage temperature -55 ~ +150 Power dissipation Short circuit current Note :...
  • Page 160 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, T = 0 to 70°C) Version Parameter Symbol Test Condition Unit Note Burst length = 1 Operating current ≥ t (min) (One bank active) = 0 mA CKE ≤...
  • Page 161 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, T = 0 to 70°C) Version Parameter Symbol Test Condition Unit Note Burst length = 1 Operating current ≥ t (min) (One bank active) = 0 mA CKE ≤...
  • Page 162 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM AC OPERATING TEST CONDITIONS = 3.3V ± 0.3V, T = 0 to 70°C) Parameter Value Unit Input levels (Vih/Vil) 2.4/0.4 Input timing measurement reference level Input rise and fall time tr/tf = 1/1 Output timing measurement reference level Output load condition See Fig.
  • Page 163 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) - 60 (x16 only) - 75 Parameter Symbol Unit Note CAS latency=3 CLK cycle 1000 1000 time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3...
  • Page 164 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM IBIS SPECIFICATION 66MHz and 100MHz/133MHz Pull-up Characteristics (Pull-up) 100MHz 100MHz 66MHz Voltage 133MHz 133MHz -100 I (mA) I (mA) I (mA) 3.45 -2.4 -200 -27.3 -74.1 -0.7 -21.1 -129.2 -7.5 -300 -34.1 -153.3 -13.3 -58.7...
  • Page 165 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Minimum V clamp current Clamp @ CLK, CKE, CS, DQM & DQ (Referenced to V I (mA) 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 Voltage I (mA) Minimum V clamp current Clamp @ CLK, CKE, CS, DQM &...
  • Page 166 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn Note Register Mode register set OP code Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Row address Read &...
  • Page 167 This datasheet has been downloaded from: www.EEworld.com.cn Free Download Daily Updated Database 100% Free Datasheet Search Site 100% Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www.EEworld.com.cn All Datasheets Cannot Be Modified Without Permission Copyright © Each Manufacturing Company...
  • Page 168 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 3-W STEREO AUDIO POWER AMPLIFIER WITH ADVANCED DC VOLUME CONTROL FEATURES DESCRIPTION • Advanced DC Volume Control With 2-dB The TPA6011A4 is a stereo audio power amplifier Steps that drives 3 W/channel of continuous RMS power From -40 dB to 20 dB into a 3-Ω...
  • Page 169 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 AVAILABLE OPTIONS PACKAGE 24-PIN TSSOP (PWP) 40°C to 85°C TPA6011A4PWP (1) The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA6011A4PWPR).
  • Page 170 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 ELECTRICAL CHARACTERISTICS = 25°C, V = PV = 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT = 5.5 V, Gain = 0 dB, SE/BTL = 0 V Output offset voltage (measured differentially) = 5.5 V, Gain = 20 dB, SE/BTL = 0 V PSRR Power supply rejection ratio...
  • Page 171 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 PWP PACKAGE (TOP VIEW) PGND ROUT+ ROUT- SE/BTL HP/LINE RHPIN VOLUME RLINEIN SEDIFF SEMAX AGND BYPASS LLINEIN FADE LHPIN SHUTDOWN LOUT+ LOUT- PGND Terminal Functions TERMINAL DESCRIPTION NAME PGND 1, 13 Power ground LOUT- Left channel negative audio output...
  • Page 172 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 FUNCTIONAL BLOCK DIAGRAM RHPIN RLINEIN HP/LINE ROUT+ ROUT- SE/BTL SE/BTL Control HP/LINE PGND Power VOLUME BYPASS 32-Step Management SEDIFF Volume SHUTDOWN SEMAX Control AGND FADE LHPIN LLINEIN HP/LINE LOUT+ LOUT- SE/BTL NOTE: All resistor wipers are adjusted with 32 step volume control.
  • Page 173 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Table 1. DC Volume Control (BTL Mode, V = 5 V) VOLUME (PIN 21) GAIN OF AMPLIFIER (Typ) FROM (V) TO (V) 0.00 0.26 0.33 0.37 0.44 0.48 0.56 0.59 0.67 0.70 0.78...
  • Page 174 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Table 2. DC Volume Control (SE Mode, V = 5 V) SE_VOLUME = VOLUME - SEDIFF or SEMAX GAIN OF AMPLIFIER (Typ) FROM (V) TO (V) 0.00 0.26 0.33 0.37 0.44 0.48 0.56...
  • Page 175 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Frequency 1, 2 3 THD+N Total harmonic distortion plus noise (BTL) vs Output power 6, 7, 8 vs Frequency 4, 5 THD+N Total harmonic distortion plus noise (SE) vs Output power vs Output voltage Closed loop response...
  • Page 176 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (SE) FREQUENCY FREQUENCY = 5 V = 5 V = 8 Ω = 32 Ω Gain = 20 dB Gain = 14 dB = 0.25 W = 0.5 W...
  • Page 177 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL) OUTPUT POWER OUTPUT POWER = 5 V = 5 V = 4 Ω = 8 Ω Gain = 20 dB Gain = 20 dB 20 kHz 20 kHz...
  • Page 178 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE = 5 Vdc = 8 Ω Gain Mode = BTL Gain = 0 dB Gain −10 −10 −20 −20 Phase Phase −30 −30 −30 −30 −40 −40...
  • Page 179 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 SUPPLY CURRENT SUPPLY CURRENT SUPPLY VOLTAGE SUPPLY VOLTAGE Mode = SD Mode = SE SHUTDOWN = 0 V = 125°C SHUTDOWN = V = 125°C = 25°C = 25°C = −40°C =−40°C 1 1.5 3 3.5...
  • Page 180 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 OUTPUT POWER OUTPUT POWER LOAD RESISTANCE LOAD RESISTANCE = 5 V = 5.5 V THD+N = 1% Gain = 20 dB Gain = 20 dB THD+N = 10% THD+N = 1% −...
  • Page 181 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 HP/LINE ATTENUATION POWER SUPPLY REJECTION RATIO (BTL) FREQUENCY FREQUENCY = 5 V −10 = 5 V = 1 V −10 = 8 Ω = 8 Ω −20 =0.47 µF (BYP) −30 −20 −40...
  • Page 182 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 OUTPUT NOISE VOLTAGE FREQUENCY = 5 V BW = 22 Hz to 22 kHz = 8 Ω Gain = 20 dB Gain = 0 dB 10 k 20 k f − Frequency − Hz Figure 27.
  • Page 183 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 APPLICATION INFORMATION SELECTION OF COMPONENTS Figure 28 and Figure 29 are schematic diagrams of typical notebook computer application circuits. Right Speaker ROUT+ PGND 100 kΩ SE/BTL ROUT- 100 kΩ HP/LINE 1 kΩ...
  • Page 184 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 APPLICATION INFORMATION (continued) Right Speaker ROUT+ PGND 100 kΩ SE/BTL ROUT- 100 kΩ HP/LINE 1 kΩ Power Supply RHPIN VOLUME In From DAC Right Negative RLINEIN SEDIFF Differential Input Signal Potentiometer (DC Voltage) Right Positive...
  • Page 185 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 APPLICATION INFORMATION (continued) RHPIN RLINEIN ROUT+ Input HP/LINE Bypass Control Bypass 330 µF ROUT- 1 kΩ 100 kΩ Bypass 100 kΩ SE/BTL LOUT+ Figure 30. TPA6011A4 Resistor Divider Network Circuit Using a 1/8-in.
  • Page 186 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Table 3. HP/LINE, SE/BTL, and Shutdown Functions INPUTS AMPLIFIER STATE HP/LINE SE/BTL SHUTDOWN INPUT OUTPUT Mute High Line High High Line High High High High High (1) Inputs should never be left unconnected. FADE OPERATION For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown.
  • Page 187 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Device Shutdown Device Shutdown ROUT+ ROUT+ Figure 31. Shutdown Sequence in the Figure 32. Shutdown Sequence in the Fade-on Mode Fade-off Mode VOLUME, SEDIFF, AND SEMAX OPERATION Three pins labeled VOLUME, SEDIFF, and SEMAX control the BTL volume when driving speakers and the SE volume when driving headphones.
  • Page 188 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 actually changes, is different depending on whether the voltage is increased or decreased as a result of the hysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing.
  • Page 189 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 INPUT RESISTANCE Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency also changes by over six times.
  • Page 190 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 POWER SUPPLY DECOUPLING, C The TPA6011A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
  • Page 191 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 As Table 4 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate, headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this applications section.
  • Page 192 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which is loudness that can be heard.
  • Page 193 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 DD(avg) (LRMS) Figure 38. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations.
  • Page 194 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Table 5. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems OUTPUT POWER EFFICIENCY PEAK VOLTAGE INTERNAL DISSIPATION 0.25 31.4 2.00 0.55 0.50 44.4 2.83 0.62 1.00 62.8 4.00 0.59 1.25 70.2 4.47...
  • Page 195 TPA6011A4 www.ti.com SLOS392A – FEBRUARY 2002 – REVISED JULY 2004 Table 6. TPA6011A4 Power Rating, 5-V, 3-Ω Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT POWER (W/Channel) TEMPERATURE 2 W (3 dB) -3°C 1 W (6 dB) 6°C 500 mW (9 dB) 24°C 250 mW (12 dB)
  • Page 196 THERMAL PAD MECHANICAL DATA www.ti.com PWP (R-PDSO-G24) THERMAL INFORMATION This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink.
  • Page 198 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
  • Page 199 AIC1117 800mA Low Dropout Positive Adjustable Regulator FEATURES DESCRIPTION Dropout Voltage 1.2V at 800mA Output Current. The AIC1117 is a low dropout three terminal Fast Transient Response. regulator with 800mA output current capability. Line Regulation typically at 0.015%. The output voltage is adjustable with the use Load Regulation typically at 0.1%.
  • Page 200 AIC1117 ORDERING INFORMATION AIC1 117-XXXX ORDER NUMBER PIN CONFIGURATION PACKAGING TYPE AIC1117CE FRONT VIEW E: TO-252 (TO-2 52) M: TO-263 1: ADJ (GND) T: TO-220 2: VOUT (TAB) Y: SOT-223 3: VIN TEMPERATURE RANGE C: 0 ° C~+70 ° C AIC1 117CM FRONT VIEW (TO-263)
  • Page 201 AIC1117 ELECTRICAL CHARACTERISTICS =5V, T =25°C, I =10mA, Unless otherwise specified) PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT Reference Voltage AIC1117 (Adj.) =25°C 1.238 1.25 1.262 ≤125°C 0°C≤T 1.225 1.25 1.275 Output Voltage AIC1117-28, V 2.82 2.85 2.88 AIC1117-33, V 3.26 3.30 3.33...
  • Page 202 AIC1117 TYPICAL PERFORMANCE CHARACTERISTICS Load Transient Response Line Transient Response 0.05 -0.05 --50 =10 µ F (Tantalum) =1 µ F -0.1 --100 =3.3V =10 µ F (Tantalum) =3.3V 0.4A 0.1A Time ( µ S) Time ( µ S) Dropout Voltage (VOUT=3.3V) Minimum Operating Current 1.19 1.18...
  • Page 203 AIC1117 BLOCK DIAGRAM Current Amp. 1.25V Thermal Current Limit Limit 55 µ A For fixed voltage device PIN DESCRIPTIONS ADJ PIN Providing V =1.25V (typ.) for adjustable V and I =55µA (typ.) (GND PIN - Power ground.) VOUT PIN - Adjustable output voltage.
  • Page 204 AIC1117 l TO-252 (unit: mm) SYMBOL 2.19 2.38 1.02 1.27 0.64 0.88 5.21 5.46 0.46 0.58 5.33 5.59 6.35 6.73 2.28 (TYP.) 9.40 10.42 0.51 l SOT-223 SYMBOL 0.02 0.12 ° 0.60 0.80 13 ° ± 3 2.90 3.15 0.24 0.35 6.30 6.80...
  • Page 205 AIC1117 l TO-263 (unit: mm) SYMBOL 4.06 4.83 0.50 1.00 1.14 1.40 1.14 1.40 8.63 9.66 9.65 10.29 2.54 (TYP.) 14.60 15.88 2.28 2.80 1.40...

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