Main(Reg) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(REG) SCHEMATIC DIAGRAM

0 1
TO MAIN IF(CN101) BATT_CHK
TO MAIN IF(CN101),
BATT_+
JACK
TO JACK ADP_DC
TO CPU
CHRG_EVR
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-23(No.YF124)
MAIN(REG)
L6001
OPEN
L6002
OPEN
!
F6001
NMFZ007-2R5X-K
C6003 C6005
OPEN 1
R6708
15k
R6713
100k
R6715
4.7k
R6717
18k
C6707
820p
C6509 R6512
0.033 47k
C6203
0.001
R6709
110k
TL6001
C6703 R6710
OPEN 120k
R6711
OPEN
IN7-
FB7
C6704
R6712
0.0047
560
IN6C-
FB6C
C6705 R6714
0.01 470
IN6-
FB6
C6706 R6716
220p 8.2k
IN5-
FB5
C6510 R6513
0.0047 27k
IN4+
IN4-
C6405
0.01
FB4
IN3+
IN3-
C6305
0.1
FB3
IN2-
FB2
C6204 R6204
220p 8.2k
R6103
8.2k
C6103
220p
R6803
1k
C6104 C6804
680p 0.0039
TL6002
IN12-
FB12
R6105
12k
OUT12
OUT11
OUT10
OUT7S
OUT6S
IC6001
OUT6P
FA7737F
OUT5P
OUT4P
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
PGND1
TL6003
C6011
1
R6007
OPEN
D6
RB551V
L6802 L6801 µ
OPEN
47
NQL365K-470X
C
R6106
100k
Q6103
C6105
RSR025P03-X
S
0.01
G
C
0
D
C
0
R6107 R6108 C
24k 36k
_0.5% _0.5%
C6107
0.022
R6110
3.3k