JVC KT-DB1000 Service Manual page 9

Pin No.
QQ
52 DDOWMSC
3 7 63 1515 0
53
54
55~60 DDOMNO0~DDOMNO5
61 DDOWFIC
62
63
64
65
66
67 MPUCLK
68 NMPUEN
69 MPUMOD
70 MDSPMO0
71 MDSPMO1
72
73
74 MDSPMO2
75 MDSPMO3
76~79 SDSPMO0~SDSPMO3
TE
L 13942296513
80
81
82
83
84
85
86
87
88
89 MCLKEN
90
91
92 PWMVCXO
93
94
95~100 TEST0~TEST5
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Symbol I/O
O
LVDD1 -
VSS3 -
O
O
VDD1 -
VSS4 -
NIRQ O
MPUTX O
MPURX I
I
I
I
O
O
MVDD0 -
MVSS0 -
O
O
O
MVDD1 -
MVSS1 -
VSS5 -
LON -
VDD2 -
VDD3 -
VOUT0 -
VOUT1 -
NRST I
I
MCLK24 I
MCLKO O
O
LVDD2 -
VSS6 -
I
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y
i
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Direct data output MSC window output terminal.
8
Internal digital VDD terminal.
Digital VSS terminal.
DIrect data output MSC sub channel ID output terminal.
Direct data output FIC window output terminal.
External digital VDD terminal.
Digital VSS terminal.
Interllupt request output terminal.
MPU interface serial data output terminal.
MPU interface serial data input terminal.
MPU interface serial clock input terminal.
MPU interface chip enable input terminal.
MPU interface mode signal input terminal.
MDSP status monitor output 0 terminal.
MDSP status monitor output 1 terminal.
DRAM VDD terminal.
DRAM VSS terminal.
MDSP status monitor output 2 terminal.
MDSP status monitor output 3 terminal.
SDSP status monitor output terminal.
Q Q
3 6 7 1 3
DRAM VDD terminal.
DRAM VSS terminal.
Digital VSS terminal.
Internal onchip power switch input terminal.
External digital VDD terminal.
External digital VDD terminal.
Onchip power supply output terminal.
Onchip power supply output terminal.
Master reset input terminal.
Master clock enable input terminal.
Mster clock input terminal.(24.576 MHz)
Master clock oscillation output terminal.
PWM output terminal for mastewr clock VCXO.
Internal digital VDD terminal.
Digital VSS terminal.
Test mode setting terminal.
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Function
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
co
KT-DB1000
9 9
2 8 9 9
9