Allwinner A20 User Manual
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Allwinner A20 User Manual

Allwinner a20 processor user manual
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Table of Contents

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A20
User Manual
Revision 1.2
Dec. 10, 2013
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

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Summary of Contents for Allwinner A20

  • Page 1 User Manual Revision 1.2 Dec. 10, 2013 Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

  • Page 2: Declaration

    Declaration THIS A20 USER MANUAL IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER. THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE.

  • Page 3: Revision History

    Description March 22, 2013 Initial version September 17, 2013 Modify TVD and TVE description December 10, 2013 Add CAN register description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 3 / 812...

  • Page 4: Table Of Contents

    Audio Codec Block Diagram ................. 172 1.13.3. Audio Codec Register List ..................172 1.13.4. Audio Codec Register Description ................ 173 1.14. LRADC ..........................190 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 4 / 812...
  • Page 5 CSI0 Register Description .................... 360 4.2. CSI1 ............................. 388 4.2.1. Overview ........................388 4.2.2. CSI1 Block Diagram ..................... 389 4.2.3. CSI1 Description ......................389 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 5 / 812...
  • Page 6 UART Special Requirement ..................627 6.5. PS2 ............................630 6.5.1. Overview ........................630 6.5.2. PS2 Block Diagram ...................... 631 6.5.3. PS2 Timing Diagram ....................631 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 6 / 812...
  • Page 7 Smart Card Reader Timing Diagram ..............770 6.14.4. Smart Card Reader Register List ................. 770 6.14.5. Smart Card Reader Register Description ............. 771 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 7 / 812...
  • Page 8 Keypad Interface Register List ................803 6.17.3. Keypad Interface Register Description ..............803 6.17.4. Keypad Interface Special Requirement ..............806 Appendix A ..............................807 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 8 / 812...

  • Page 9: Chapter 1 System

    System Chapter 1 This part details the A20 system construction from following aspects:  OVERVIEW  A20 BLOCK DIAGRAM  MEMORY MAPPING  CPU CONFIGURATION  CCU  BOOT SYSTEM  SYSTEM CONTROL  PWM  TIMER  HIGH SPEED TIMER ...

  • Page 10: Overview

    Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and smart TV applications. A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also integrates the powerful ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good game compatibility.
  • Page 11 – Support 1GB/2GB/4GB/8GB/16GB/32GB/64GB /128GB SD/MMC card – Support SDIO interrupt detection – Support descriptor-based internal DMA controller for efficient scatter and gather operations A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 11 / 812...

  • Page 12: System Resources

    – Supported formats: Mpeg1/2, Mpeg4 SP/ASP GMC, H.263 including Sorenson Spark, H.264 BP/MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc. ● Video Encoding – H.264 HP up to 1080p@30fps A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 12 / 812...

  • Page 13: Video Output

    ● Stereo audio DAC ● Stereo capless headphone drivers – Up to 100dB SNR during DAC playback – Support 8KHz~192KHz DAC sample rate A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 13 / 812...

  • Page 14: Analog Audio Input

    ● Support 10/100/1000Mbps data transfer rates RGMII interface to communicate with an external Gigabit ● Support 10/100Mbps MII PHY interface Digital Audio In/Out A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 14 / 812...
  • Page 15 ● Two PS2 compliant to IBM PS2 and AT-compatible keyboard and mouse interface ● Dual-role controller: a PS2 host or a PS2 device ● A flexible receiver for IR remote control A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 15 / 812...

  • Page 16: Power Management

    ● Flexible PLL clock generator and OSC for 32KHz ● Flexible clock gate ● Support DVFS for CPU frequency and voltage adjustment A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 16 / 812...
  • Page 17 ● Support standby mode (only DDR+RTC-Domain power exist) Package ● FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 17 / 812...

  • Page 18: A20 Block Diagram

    1.2. A20 Block Diagram The follow figure shows the block diagram of the A20. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 18 / 812...

  • Page 19: Memory Mapping

    0x01C0 E000---0x01C0 EFFF SD/MMC 0 0x01C0 F000---0x01C0 FFFF SD/MMC 1 0x01C1 0000---0x01C1 0FFF SD/MMC 2 0x01C1 1000---0x01C1 1FFF SD/MMC 3 0x01C1 2000---0x01C1 2FFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 19 / 812...
  • Page 20 0x01C2 3000---0x01C2 33FF 0x01C2 3400---0x01C2 37FF 0x01C2 3800---0x01C2 3BFF SJTAG 0x01C2 3C00---0x01C2 3FFF 0x01C2 4000---0x01C2 43FF IIS-2 0x01C2 4400---0x01C2 47FF 0x01C2 4800---0x01C2 4BFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 20 / 812...
  • Page 21 TWI 3 0x01C2 B800---0x01C2 BBFF 0x01C2 BC00---0x01C2 BFFF TWI 4 0x01C2 C000---0x01C2 C3FF Smart Card Reader 0x01C2 C400---0x01C2 C7FF 0x01C3 0000---0x01C3 FFFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 21 / 812...
  • Page 22 0x01E8 0000---0x01E9 FFFF 128K 0x01EA 0000---0x01EB FFFF 128K CoreSight Debug Module 0x3F50 0000---0x3F50 FFFF DDR-II/DDR-III 0x4000 0000---0xBFFF FFFF BROM 0xFFFF 0000—0xFFFF 7FFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 22 / 812...

  • Page 23: Cpu Configuration

     Software reset control for each individual CPU  CPU configuration for each individual CPU  Three 64-bit idle counters and two 64-bit common counters A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 23 / 812...

  • Page 24: Cpu Configuration Register List

    64-bit Counter High Register LOSC_CNT64_CTRL_REG 0x0290 64-bit Counter Control Register LOSC_CNT64_LOW_REG 0x0294 64-bit Counter Low Register LOSC_CNT64_HIGH_REG 0x0298 64-bit Counter High Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 24 / 812...

  • Page 25: Cpucfg Register Description

    Offset: 0x44 Register Name: CPU0_CTRL_REG Read/ Default/Hex Description Write 31:1 CPU0_CP15_WRITE_DISABLE. Disable write access to certain CP15 registers. 0: enable 1: disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 25 / 812...
  • Page 26 CPU Debug, and breakpoint and watch point logic in the processor power domains. They do not reset debug logic in the debug power domain. 0: assert 1: de-assert. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 26 / 812...
  • Page 27 0: AMP mode 1: SMP mode 1.4.3.7. GENERAL CONTROL REGISTER(DEFAULT :0X00000020) Offset: 0x184 Register Name: GENER_CTRL_REG Read/ Default/Hex Description Write 31:9 CFGSDISABLE. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 27 / 812...
  • Page 28 Event input that can wake-up CPU0/1 from WFE standby mode. 1.4.3.9. PRIVATE REGISTER (DEFAULT: 0X00000000) Offset: 0x1A4 Register Name: PRIVATE_REG Read/ Default/Hex Description Write 31:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 28 / 812...
  • Page 29 0: no effect, 1: to latch the idle Counter to the Low/Hi registers and it will change to zero after the registers are latched. IDLE_CNT_CLR_EN. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 29 / 812...
  • Page 30 IDLE COUNTER 1 CONTROL REGISTER (DEFAULT: 0X00000000) Offset: 0x218 Register Name: IDLE_CNT1_CTRL_REG Read/ Default/Hex Description Write 31:3 IDLE_CNT_EN. Idle counter enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 30 / 812...
  • Page 31 CNT64_CLR_EN. 64-bit Counter Clear Enable. 0: no effect, 1: to clear the 64-bit Counter Low/Hi registers and A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 31 / 812...
  • Page 32 0: no effect, 1: to latch the 64-bit Counter to the Low/Hi registers and it will change to zero after the registers are A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 32 / 812...
  • Page 33 1.4.3.21. LOSC 64-BIT COUNTER HIGH REGISTER (DEFAULT: 0X00000000) Offset: 0x298 Register Name: LOSC_CNT64_HIGH_REG Default/H Read/Write Description CNT64_HI. 31:0 64-bit Counter [63:32]. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 33 / 812...

  • Page 34: Ccu

    The CCU (Clock Control Unit) is made up of 8 PLLs, a main oscillator, an on-chip RC oscillator and a 32768Hz low-power oscillator. A20 integrates two crystal oscillators: The 24MHz crystal is mandatory, which is used to provide clock source for the PLL and the main digital blocks, and the 32768Hz oscillator, which is only used to provide a low power, accurate reference for the RTC.

  • Page 35: Clock Tree Diagram

    0x01C20000 Register Name Offset Description PLL1_CFG_REG 0x0000 PLL1 CONTROL PLL1_TUN_REG 0x0004 PLL1 TUNING PLL2_CFG_REG 0x0008 PLL2 CONTROL PLL2_TUN_REG 0x000C PLL2 TUNING A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 35 / 812...
  • Page 36 SECURITY SYSTEM CLOCK REGISTER SPI0_CLK_REG 0x00A0 SPI0 CLOCK REGISTER SPI1_CLK_REG 0x00A4 SPI1 CLOCK REGISTER SPI2_CLK_REG 0x00A8 SPI2 CLOCK REGISTER IR0_CLK_REG 0x00B0 IR0 CLOCK REGISTER A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 36 / 812...
  • Page 37 AUDIO_CODEC_CLK_REG 0x0140 AUDIO CODEC CLOCK REGISTER AVS_CLK_REG 0x0144 AVS CLOCK REGISTER ACE_CLK_REG 0x0148 ACE CLOCK REGISTER LVDS_CLK_REG 0x014C LVDS CLOCK REGISTER A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 37 / 812...

  • Page 38: Ccu Register Description

    240MHz~2GHz if the bypass is disabled. Its default is 384MHz. 29:26 EXG_MODE. Exchange mode. 24:20 19:18 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 38 / 812...
  • Page 39 1.5.4.2. PLL1-TUNING(DEFAULT: 0X0A101000) Offset: 0x04 Register Name: PLL1_TUN_REG Read/ Default/Hex Write Description 31:0 1.5.4.3. PLL2-AUDIO(DEFAULT: 0X08100010) Offset: 0x08 Register Name: PLL2_CFG_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 39 / 812...
  • Page 40 PLL2 Factor N. Factor=0, N=1; 14:8 Factor=1, N=1; …… Factor=0x7F, N=0x7F; PLL2_PRE_DIV. PLL2 pre-dividor[4:0]. PLL2_PRE_DIV=divider 0x10 00000: 0x1 00001: 0x1 …… 11111: 0x1F A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 40 / 812...
  • Page 41 In the integer mode, The PLL3 output=3MHz*M. In the fractional mode, the PLL3 output is selected by bit 14. The PLL3 output range is 27MHz~381MHz. 30:27 26:24 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 41 / 812...
  • Page 42 PLL4 Output Bypass Enable. 0: Disable, 1: Enable. If the bypass is enabled, the PLL4 output is 24MHz. 29:25 24:20 19:16 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 42 / 812...
  • Page 43 Note: the output 24MHz*N*K clock must be in the range of 240MHz~2GHz if the bypass is disabled. DDR_CLK_OUT_EN. DDR clock output en. 28:25 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 43 / 812...
  • Page 44 PLL5 Factor M.(M = Factor + 1 ) The range is from 1 to 4. 1.5.4.8. PLL5-TUNING(DEFAULT: 0X14888000) Offset: 0x24 Register Name: PLL5_TUN_REG Read/ Default/Hex Write Description 31:29 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 44 / 812...
  • Page 45 PLL6 Output Bypass Enable. 0: Disable, 1: Enable. If the bypass is enabled, the PLL6 output is 24MHz. 29:25 24:20 19:16 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 45 / 812...
  • Page 46 1.5.4.10. PLL6-TUNING Offset: 0x2C Register Name: PLL6_TUN_REG Read/ Default/Hex Description Write 31:0 1.5.4.11. PLL7-VIDEO 1(DEFAULT: 0X0010D063) Offset: 0x30 Register Name: PLL7_CFG_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 46 / 812...
  • Page 47 Sigma-delta pattern enable. SPR_FREQ_MODE. Spread Frequency Mode. 00: DC=0 30:29 01: DC=1 10: Triangular 11: awmode WAVE_STEP. 28:20 Wave step. 18:17 FREQ. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 47 / 812...
  • Page 48 11: awmode WAVE_STEP. 28:20 Wave step. FREQ. Frequency. 00: 31.5KHz 18:17 01: 32KHz 10: 32.5KHz 11: 33KHz WAVE_BOT. 16:0 Wave Bottom. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 48 / 812...
  • Page 49 1.5.4.15. OSC24M (DEFAULT: 0X00138013) Offset: 0x50 Register Name: OSC24M_CFG_REG Read/ Default/Hex Write Description KEY_FIELD. 31:24 Key Field for LDO Enable bit. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 49 / 812...
  • Page 50 11: 200MHz(source from the PLL6). If the clock source is changed, at most to wait for 8 present running clock cycles. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 50 / 812...
  • Page 51 Note: System ATB/APB clock source is CPU clock source. AXI_CLK_DIV_RATIO. AXI Clock divide ratio. AXI Clock source is CPU clock. 00: /1 01: /2 10: /3 11: /4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 51 / 812...
  • Page 52 Read/ Default/Hex Description Write 31:29 STIMER_AHB_GATING Gating AHB Clock for Sync timer(0:mask,1:pass) 27:26 Gating AHB Clock for SATA(0: mask, 1: pass). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 52 / 812...
  • Page 53 Gating AHB Clock for USB0(0: mask, 1: pass). 1.5.4.19. AHB MODULE CLOCK GATING REGISTER 1(DEFAULT: 0X00000000) Offset: 0x64 Register Name: AHB_GATING_REG1 Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 53 / 812...
  • Page 54 APB0 MODULE CLOCK GATING(DEFAULT: 0X00000000) Offset: 0x68 Register Name: APB0_GATING_REG Read/ Default/He Description Write 31:11 KEYPAD_APB_GATING. Gating APB Clock for Keypad(0: mask, 1: pass). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 54 / 812...
  • Page 55 Gating APB Clock for UART7(0: mask, 1: pass). UART6_APB_GATING. Gating APB Clock for UART6(0: mask, 1: pass). UART5_APB_GATING. Gating APB Clock for UART5(0: mask, 1: pass). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 55 / 812...
  • Page 56 Gating APB Clock for TWI2(0: mask, 1: pass). TWI1_APB_GATING. Gating APB Clock for TWI1(0: mask, 1: pass). TWI0_APB_GATING. Gating APB Clock for TWI0(0: mask, 1: pass). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 56 / 812...
  • Page 57 Note: In practice, the module clock frequency is always switched off. 1.5.4.23. MS CLOCK(DEFAULT: 0X00000000) Offset: 0x84 Register Name: MS_SCLK_CFG_REG Read/ Default/Hex Description Write SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 57 / 812...
  • Page 58 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/Divider N/Divider M. 30:26 CLK_SRC_SEL. 25:24 Clock Source Select A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 58 / 812...
  • Page 59 Register Name: SD1_CLK_REG Read/ Default/Hex Description Write SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 59 / 812...
  • Page 60 The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 1.5.4.26. SD/MMC 2 CLOCK(DEFAULT: 0X00000000) Offset: 0x90 Register Name: SD2_CLK_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 60 / 812...
  • Page 61 0 to 7. CLK_DIV_RATIO_M. Clock divide ratio (m) The pre-divided clock is divided by (m+1). The divider is from 1 to 16. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 61 / 812...
  • Page 62 0 to 7. CLK_DIV_RATIO_M. Clock divide ratio (m) The pre-divided clock is divided by (m+1). The divider is from 1 to 16. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 62 / 812...
  • Page 63 Register Name: SS_CLK_REG Read/ Default/Hex Description Write SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 63 / 812...
  • Page 64 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/Divider N/Divider M. 30:26 CLK_SRC_SEL. 25:24 Clock Source Select 00: OSC24M A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 64 / 812...
  • Page 65 30:26 CLK_SRC_SEL. Clock Source Select 00: OSC24M 25:24 01: PLL6 10: PLL5 11: /. 23:18 CLK_DIV_RATIO_N. 17:16 Clock pre-divide ratio (n) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 65 / 812...
  • Page 66 The select clock source is pre-divided by 2^n. The divider is 1/2/4/8. 15:4 CLK_DIV_RATIO_M. Clock divide ratio (m) The pre-divided clock is divided by (m+1). The divider is from 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 66 / 812...
  • Page 67 The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 1.5.4.34. IR 1 CLOCK(DEFAULT: 0X00000000) Offset: 0xB4 Register Name: IR1_CLK_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 67 / 812...
  • Page 68 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON 30:18 CLK_SRC_SEL. 17:16 00: PLL2 (8x) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 68 / 812...
  • Page 69 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/Divider N/Divider M. 30:26 CLK_SRC_SEL. 25:24 Clock Source Select 0: OSC24M A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 69 / 812...
  • Page 70 CLK_SRC_GATING. Clock Source Select 0: PLL6 for SATA(100MHz) 1: External Clock 23:0 1.5.4.39. USB CLOCK(DEFAULT: 0X00000000) Offset: 0xCC Register Name: USB_CLK_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 70 / 812...
  • Page 71 1: Reset invalid 1.5.4.40. SPI3 CLOCK(DEFAULT: 0X00000000) Offset: 0xD4 Register Name: SPI3_CLK_REG Read/ Default/Hex Description Write SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 71 / 812...
  • Page 72 Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON 30:18 CLK_SRC_SEL. 17:16 00: PLL2 (8x) 01: PLL2(4X) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 72 / 812...
  • Page 73 Gating DRAM Clock for ACE(0: mask, 1: pass). DE_MP_DCLK_GATING. Gating DRAM Clock for DE_MP(0: mask, 1: pass). BE1_DCLK_GATING. Gating DRAM Clock for DE_BE1(0: mask, 1: pass). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 73 / 812...
  • Page 74 Gating DRAM Clock for VE(0: mask, 1: pass). 1.5.4.44. DE-BE 0 CLOCK(DEFAULT: 0X00000000) Offset: 0x104 Register Name: BE0_SCLK_CFG_REG Read/ Default/Hex Description Write SCLK_GATING. Gating Special Clock A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 74 / 812...
  • Page 75 This special clock = Clock Source/Divider M. BE1_RST. DE-BE1 Reset. 0: reset valid, 1: reset invalid. 29:26 CLK_SRC_SEL. 25:24 Clock Source Select A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 75 / 812...
  • Page 76 10: PLL5 11: /. 23:4 CLK_DIV_RATIO_M. Clock divide ratio (m) The pre-divided clock is divided by (m+1). The divider is from A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 76 / 812...
  • Page 77 The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 1.5.4.48. DE-MP CLOCK(DEFAULT: 0X00000000) Offset: 0x114 Register Name: MP_CLK_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 77 / 812...
  • Page 78 0: Clock is OFF 1: Clock is ON This special clock = Clock Source LCD0_RST. LCD0 Reset. 0: reset valid, 1: reset invalid. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 78 / 812...
  • Page 79 0: reset valid, 1: reset invalid. 29:26 CLK_SRC_SEL. Clock Source Select 00: PLL3(1X) 25:24 01: PLL7(1X) 10: PLL3(2X) 11: PLL7(2X) 23:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 79 / 812...
  • Page 80 This special clock = Clock Source/ CLK_DIV_RATIO1_M. Gating Special Clock 1 should be ON at the same time. 30:20 19:16 CLK_DIV_RATIO2_M. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 80 / 812...
  • Page 81 This special clock 2= Special Clock 2 Source/Divider M. 30:26 SCLK2_SEL. Special Clock 2 Source Select 00: PLL3(1X) 25:24 01: PLL7(1X) 10: PLL3(2X) 11: PLL7(2X) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 81 / 812...
  • Page 82 This special clock 2= Special Clock 2 Source/Divider M. 30:26 SCLK2_SRC_SEL. Special Clock 2 Source Select 00: PLL3(1X) 25:24 01: PLL7(1X) 10: PLL3(2X) 11: PLL7(2X) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 82 / 812...
  • Page 83 This special clock = Clock Source/Divider M. CSI0_RST. CSI0 Reset. 0: reset valid, 1: reset invalid. 29:27 CLK_SRC_SEL. 26:24 Clock Source Select A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 83 / 812...
  • Page 84 0: reset valid, 1: reset invalid. 29:27 Clock Source Select 000: OSC24M 001: PLL3(1X) 26:24 010: PLL7(1X) 011: / 100: / A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 84 / 812...
  • Page 85 VE Reset. 0: reset valid, 1: reset invalid. 1.5.4.58. AUDIO CODEC CLOCK(DEFAULT: 0X00000000) Offset: 0x140 Register Name: AUDIO_CODEC_CLK_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 85 / 812...
  • Page 86 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/Divider M. 30:25 CLK_SRC_SEL. Clock Source Select 0: PLL4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 86 / 812...
  • Page 87 Gating Special Clock 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/ Divider M 30:26 25:24 CLK_SRC_SEL. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 87 / 812...
  • Page 88 0: reset valid, 1: reset invalid 29:27 CLK_SRC_SEL. Clock Source Select 000: PLL3 001: PLL4 26:24 010: PLL5 011: PLL7 100: PLL8 101:/ 110:/ A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 88 / 812...
  • Page 89 The select clock source is pre-divided by 2^N. The divider is 1/2/4/8. 15:4 MBUS_SCLK_RATIO_M Clock Divide Ratio (M) The divided clock is divided by (M+1). The divider is from 1 to A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 89 / 812...
  • Page 90 0: MII; 1: RGMII; GTCS GMAC Transmit Clock Source 00: Transmit clock source for MII; 01: External transmit clock source(125MHz) for RGMII; A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 90 / 812...
  • Page 91 Read/ Default/Hex Description Write 31:0 HDMI1 System Control Register 1.5.4.68. HDMI1 SLOW CLOCK REGISTER (DEFAULT: 0X00000000) Offset: 0x178 Register Name: HDMI1_SLOW_CLK_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 91 / 812...
  • Page 92 The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 1.5.4.70. CLK_OUTA_REG (DEFAULT: 0X00000000) Offset: 0x1F0 Register Name: CLK_OUTA_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 92 / 812...
  • Page 93 12:8 00001: /2 00010: /3 …… 11111: /32 1.5.4.71. CLK_OUTB_REG (DEFAULT: 0X00000000) Offset: 0x1F4 Register Name: CLK_OUTB_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 93 / 812...
  • Page 94 10: /4 11: /8 19:13 DIVIDOR_M Clock Output Divide Factor M 00000: /1 12:8 00001: /2 00010: /3 …… 11111: /32 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 94 / 812...

  • Page 95: System Boot

    1.6. System Boot 1.6.1. Overview A20 supports system boot from NAND Flash, SPI NOR Flash (SPI0), SD card (SDC 0/2), and USB. After power on, the system will try to boot from SDC0, NAND Flash, SDC2, SPI0, and USB successively, but if the Boot Select Pin, or BSP, an external pin that is used to select system boot method, is checked to be in low level state, the system will direclty boot from USB.

  • Page 96: System Boot Diagram

    SDC2 Boot Success? SPI0(PC port) boot operation SPI Nor Flash Boot Success? boot OK, run other firmware USB boot operation A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 96 / 812...

  • Page 97: System Control

    D( USB ) 0x00010000—0x00010FFF B(Secure RAM) 0x00020000--0x0002FFFF CPU0 I-Cache CPU0 D-Cache CPU1 I-Cache CPU1 D-Cache CPU L2 Cache 256K Total 502K A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 97 / 812...

  • Page 98: System Control Register List

    0: map to CPU/DMA 1: map to VE 1.7.3.2. SRAM CONTROL REGISTER 1(DEFAULT: 0X00001300) Offset: 0x4 Register Name: SRAM_CTRL_REG1 Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 98 / 812...
  • Page 99 0: map to CPU/DMA 1: map to USB0 1.7.3.3. VERSION REGISTER(DEFAULT: 0X00000000) Offset: 0x24 Register Name: VER_REG Read/ Default/He Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 99 / 812...
  • Page 100 I/O is switched off, and it’s power source is RTCVDD. 00: Low level sensitive 01: Negative edge trigged 10: High level sensitive 11: Positive edge sensitive A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 100 / 812...
  • Page 101 Default/Hex Description Write 31:1 NMI_IRQ_SRC_ENABLE. NMI Source Enable and Disable Bit. 0: NMI interrupt is disable. 1: NMI interrupt is enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 101 / 812...

  • Page 102: Pwm

    PWM pulse mode, the output will be a positive pulse or a negative pulse. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 102 / 812...

  • Page 103: Pwm Register List

    1: PWM0 period register is busy. 27:25 PWM1_BYPASS. PWM CH1 bypass enable. If the bit is set to 1, PWM1’s output is OSC24MHz. 0: disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 103 / 812...
  • Page 104 0010: /240 0011: /360 18:15 0100: /480 0101: / 0110: / 0111: / 1000: /12k 1001: /24k 1010: /36k 1011: /48k A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 104 / 812...
  • Page 105 These bits should be setting before the PWM Channel 0 clock gate on. 0000: /120 0001: /180 0010: /240 0011: /360 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 105 / 812...
  • Page 106 1 = 1 cycles …… N = N cycles Note: the active cycles should be no larger than the period cycles. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 106 / 812...
  • Page 107 Number of the active cycles in the PWM clock. 0 = 0 cycle 15:0 1 = 1 cycles …… N = N cycles A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 107 / 812...

  • Page 108: Timer

    In normal operation mode, both the alarm interrupt and the power management wakeup are activated while in power-off mode, only the power management wakeup signal is activated. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 108 / 812...

  • Page 109: Timer Register List

    AVS_CNT_DIV_REG 0x8C AVS Divisor Register WDOG_CTRL_REG 0x90 Watchdog Control Register WDOG_MODE_REG 0x94 Watchdog Mode Register LOSC_CTRL_REG 0x100 Low Oscillator Control Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 109 / 812...

  • Page 110: Timer Register Description

    TMR4_IRQ_EN. Timer 4 Interrupt Enable. 0: No effect, 1: Timer 4 Interval Value reached interrupt enable. TMR3_IRQ_EN. Timer 3 Interrupt Enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 110 / 812...
  • Page 111 Timer 2 IRQ Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending, timer 2 counter value is reached. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 111 / 812...
  • Page 112 100: /16 101: /32 110: /64 111: /128 TMR0_CLK_SRC. Timer 0 Clock Source. 00: Low speed OSC, 01: OSC24M. 10: PLL6/6 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 112 / 812...
  • Page 113 Note: when you set the value, please take into consideration the system clock and the timer clock source. 1.9.3.5. TIMER 0 CURRENT VALUE REGISTER Offset: 0x18 Register Name: TMR0_CUR_VALUE_REG Read/ Default/Hex Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 113 / 812...
  • Page 114 111: /128 TMR1_CLK_SRC. Timer 1 Clock Source. 00: Low speed OSC, 01: OSC24M. 10: PLL6/6 11: /. TMR1_RELOAD. Timer 1 Reload. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 114 / 812...
  • Page 115 Note: Timer 1 current value is a 32-bit down-counter(from interval value to 0). This register can be read correctly if the PCLK is faster than 2*TimerFreq(TimerFreq = TimerClkSource/pre-scale). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 115 / 812...
  • Page 116 At least wait for 2 Tcylces, the start bit can be set to 1. In timer pause state, the interval value register can be A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 116 / 812...
  • Page 117 Offset: 0x40 Register Name: TMR3_CTRL_REG Read/ Default/Hex Description Write 31:5 TMR3_MODE. Timer 3 mode. 0: Continuous mode. When interval value reached, the A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 117 / 812...
  • Page 118 Offset: 0x50 Register Name: TMR4_CTRL_REG Read/ Default/Hex Description Write 31:8 TMR4_MODE. Timer 4 mode. 0: Continuous mode. When interval value reached, the A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 118 / 812...
  • Page 119 1 at the same time. Note: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 119 / 812...
  • Page 120 0: Continuous mode. When interval value reached, the timer will not disable automatically. 1: Single mode. When interval value reached, the timer will disable automatically. TMR5_CLK_PRES. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 120 / 812...
  • Page 121 0; 2) The time between the timer disabled and enabled should be larger than 2*Tcycles(Tcycles= Timer clock source/pre-scale). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 121 / 812...
  • Page 122 0: Not pause 1: Pause Counter 1 AVS_CNT0_PS Audio/Video Sync Counter 0 Pause Control 0: Not pause 1: Pause Counter 0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 122 / 812...
  • Page 123 The high 32 bits of the internal 33-bits counter register. The initial value of the internal 33-bits counter register can be set A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 123 / 812...
  • Page 124 1 and the 12-bits counter will reset to zero and restart again. Notes: It can be configured by software at any time. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 124 / 812...
  • Page 125 0101: 5sec 0110: 6sec 0111: 8sec 1000: 10sec 1001: 12sec 1010: 14sec 1011: 16sec 1100: / 1101: / 1110: / 1111: / A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 125 / 812...
  • Page 126 After writing the RTC YY-MM-DD register, the YY-MM-DD register will be refreshed for at most one second. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 126 / 812...
  • Page 127 Leap Year. 0: not, 1: Leap year. This bit can not set by hardware. It should be set or clear by software. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 127 / 812...
  • Page 128 011: Thursday 100: Friday 101: Saturday 110: Sunday 111: / 28:21 HOUR. 20:16 Range from 0~23 15:14 MINUTE. 13:8 Range from 0~59 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 128 / 812...
  • Page 129 Offset: 0x110 Register Name: ALARM_WK_HH_MM-SS Read/ Default/Hex Description Write 31:21 HOUR. 20:16 Range from 0~23. 15:14 MINUTE. 13:8 Range from 0~59. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 129 / 812...
  • Page 130 Week 4(Friday) Alarm Enable. 0: Disable, 1: Enable. If this bit is set to “1”, only when the Alarm Week HH-MM-SS A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 130 / 812...
  • Page 131 “1”. 1.9.3.32. ALARM IRQ ENABLE REGISTER Offset: 0x118 Register Name: ALARM_IRQ_EN Read/ Default/Hex Description Write 31:2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 131 / 812...
  • Page 132 Default/Hex Description Write TMR_GP_DATA. 31:0 Data[31:0]. Note: Timer general purpose register value can be stored if the RTCVDD is above 1.0V. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 132 / 812...
  • Page 133 Write 31:1 ALARM_WAKEUP. Configuration of alarm wake up output. 0: disable alarm wake up output; 1: enable alarm wake up output. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 133 / 812...

  • Page 134: High Speed Timer

    1.10. High Speed Timer 1.10.1. Overview The A20 supports four high speed timers, whose clock sources are fixed to AHBCLK. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 134 / 812...

  • Page 135: High Speed Timer Register List

    HS Timer 3 Interval Value High Register HS_TMR3_CURNT_LO_REG 0x7C HS Timer 3 Current Value Low Register HS_TMR3_CURNT_HI_REG 0x80 HS Timer 3 Current Value High Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 135 / 812...

  • Page 136: High Speed Timer Controller Register

    Description Write 31:4 HS_TMR3_IRQ_PEND. High Speed Timer 3 IRQ Pending. Set 1 to the bit will clear it. 0: No effect; A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 136 / 812...
  • Page 137 Select the pre-scale of the high speed timer 0 clock sources. 000: /1 001: /2 010: /4 011: /8 100: /16 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 137 / 812...
  • Page 138 High Speed Timer 0 Interval Value [31:0]. 1.10.3.5. HS TIMER 0 INTERVAL VALUE HI REGISTER Offset:0x18 Register Name: HS_TMR0_INTV_HI_REG Read/ Default/He Description Write 31:24 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 138 / 812...
  • Page 139 1.10.3.8. HS TIMER 1 CONTROL REGISTER (DEFAULT: 0X00000000) Offset:0x30 Register Name:HS_TMR1_CTRL_REG Read/ Default/H Description Write 30:8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 139 / 812...
  • Page 140 1 at the same time. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 140 / 812...
  • Page 141 1.10.3.12. HS TIMER 1 CURRENT VALUE HI REGISTER Offset:0x40 Register Name: HS_TMR1_CURNT_HI_REG Read/ Default/He Description Write 31:24 HS_TMR1_CUR_VALUE_HI. 23:0 High Speed Timer 1 Current Value [55:32]. Note: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 141 / 812...
  • Page 142 If the current counter does not reach the zero, the timer enable bit is set to “0”, the current value counter will pause. At least wait A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 142 / 812...
  • Page 143 1.10.3.16. HS TIMER 2 CURRENT VALUE LO REGISTER Offset: 0x5C Register Name: HS_TMR2_CURNT_LO_REG Read/ Default/ Description Write HS_TMR2_CUR_VALUE_LO. 31:0 High Speed Timer 2 Current Value [31:0]. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 143 / 812...
  • Page 144 Select the pre-scale of the high speed timer 3 clock sources. 000: /1 001: /2 010: /4 011: /8 100: /16 101: / 110: / 111: / HS_TMR3_RELOAD. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 144 / 812...
  • Page 145 Note: the interval value register is a 56-bit register. When read or write the interval value, the Lo register should be read or written first. And the Hi register should be written after the Lo register. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 145 / 812...
  • Page 146 2) The current value register is a 56-bit register. When read or write the current value, the Low register should be read or written first. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 146 / 812...

  • Page 147: Gic

    PPI 0 interrupt PPI 1 PPI 1 interrupt PPI 2 PPI 2 interrupt PPI 3 PPI 3 interrupt PPI 4 PPI 4 interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 147 / 812...
  • Page 148 IIS0 Digital Audio Controller 0 interrupt UART 4 UART 4 interrupt UART 5 UART 5 interrupt UART 6 UART 6 interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 148 / 812...
  • Page 149 LCD Controller 0 interrupt LCD Controller 1 LCD Controller 1 interrupt MP interrupt. DE-FE0/DE-BE0 DE-FE0/DE-BE0 interrupt DE-FE1/DE-BE1 DE-FE1/DE-BE1 interrupt PMU interrupt SPI3 SPI3 interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 149 / 812...
  • Page 150 GPU-GPMMU interrupt GPU-PP0 GPU-PP0 interrupt GPU-PPMMU0 GPU-PPMMU0 interrupt GPU-PMU GPU-PMU interrupt GPU-PP1 GPU-PP1 interrupt GPU-PPMMU1 GPU-PPMMU1 interrupt GPU-RSV0 GPU-RSV1 GPU-RSV2 GPU-RSV3 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 150 / 812...
  • Page 151 Digital Audio Controller 1 interrupt TWI 3 TWI 3 interrupt TWI 4 TWI 4 interrupt IIS 2 Digital Audio Controller 2 interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 151 / 812...

  • Page 152: Dma

    Although the increase mode of NDMA should be address aligned, but its byte counter should not be multiple. The DMA Source Address, Destination Address, Byte Counter Registers can be modified even if the DMA is started. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 152 / 812...

  • Page 153: Dma Register List

    (N=0,1,2,3,4,5,6,7) Dedicated Destination DDMA_DEST_START_ADDR_RE Start Address 0x300+N*0x20+0x8 (N=0,1,2,3,4,5,6,7) Dedicated DMA Byte Counter DDMA_BC_REG 0x300+N*0x20+0xC (N=0,1,2,3,4,5,6,7) Dedicated DMA Parameter DDMA_PARA_REG 0x300+N*0x20+0x18 (N=0,1,2,3,4,5,6,7) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 153 / 812...

  • Page 154: Dma Controller Register Description

    Dedicated DMA 3 End Transfer Interrupt Enable. 0: Disable, 1: Enable. DDMA3_HF_IRQ_EN Dedicated DMA 3 Half Transfer Interrupt Enable. 0: Disable, 1: Enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 154 / 812...
  • Page 155 Normal DMA 6 Half Transfer Interrupt Enable. 0: Disable, 1: Enable. NDMA5_END_IRQ_EN Normal DMA 5 End Transfer Interrupt Enable. 0: Disable, 1: Enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 155 / 812...
  • Page 156 Normal DMA 0 End Transfer Interrupt Enable. 0: Disable, 1: Enable. NDMA0_HF_IRQ_EN Normal DMA 0 Half Transfer Interrupt Enable. 0: Disable, 1: Enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 156 / 812...
  • Page 157 Dedicated DMA 4 Half Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. DDMA3_END_IRQ_PEND A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 157 / 812...
  • Page 158 0: No effect, 1: Pending. NDMA7_HF_IRQ_PEND. Normal DMA 7 Half Transfer Interrupt Pending. Set 1 to the bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 158 / 812...
  • Page 159 0: No effect, 1: Pending. NDMA2_END_IRQ_PEND. Normal DMA 2 End Transfer Interrupt Pending. Set 1 to the bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 159 / 812...
  • Page 160 0: NDMA auto clock gating enable 1: NDMA auto clock gating disable If NDMA works in Continuous mode, this bit should be set to 1. 15:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 160 / 812...
  • Page 161 DMA Destination Burst Length. 00: 1 24:23 01: / 10: 8 11: / DMA_DEST_SEC. DMA Destination Security 0: secure, 1: non-secure. NDMA_DEST_ADDR_TYPE. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 161 / 812...
  • Page 162 11000 : SPI0 TX 11001 : SPI1 TX 11010 : SPI2 TX 11011 : SPI3 TX 11100 : USB EP2 11101 : USB EP3 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 162 / 812...
  • Page 163 1: No Change NDMA_SRC_DRQ_TYPE. Normal DMA Source DRQ Type. 00000 : IR0-RX 00001 : IR1-RX 00010 : SPDIF-RX 00011 : IIS0-RX A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 163 / 812...
  • Page 164 NORMAL DMA SOURCE ADDRESS REGISTER(DEFAULT: 0X00000000) Offset: 0x100+N*0x20+0x4 Register Name: NDMA_SRC_ADDR_REG (N=0,1,2,3,4,5,6,7) Read/ Default/Hex Description Write NDMA_SRC_ADDR. 31:0 Normal DMA Source Address. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 164 / 812...
  • Page 165 Set 0 to the bit will stop the corresponding DMA channel and reset its state machine. DMA_BSY_STA. DMA Busy Status. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 165 / 812...
  • Page 166 Dedicated DMA Destination DRQ Type 0x0: SRAM memory 0x1: SDRAM memory 20:16 0x2: 0x3: NAND Flash Controller (NFC) 0x4: USB0 0x5: / A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 166 / 812...
  • Page 167 1 : remain mode(the value read back is equal to the remain counter to be transfered). 14:13 DMA_SRC_SEC. DMA Source Security. 0: secure, 1: non-secure. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 167 / 812...
  • Page 168 0x7: Ethernet MAC Rx 0x8: / 0x9: SPI1 RX 0xA: / 0xB: Security System Rx 0xC: / 0xD: / 0xE: / 0xF: / A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 168 / 812...
  • Page 169 1.12.3.10. DEDICATED DMA DESTINATION START ADDRESS REGISTER Offset: 0x300+N*0x20+0x8 Register Name: DDMA_DEST_START_ADDR_REG (N=0,1,2,3,4,5,6,7) Read/ Default/H Description Write DDMA_DEST_START_ADDR. 31:0 Dedicated DMA Destination Start Address. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 169 / 812...
  • Page 170 SRC_DATA_BLK_SIZE. 15:8 Source Data Block Size n. SRC_WAIT_CYC. Source Wait Clock Cycles n. Note: If the counter=N, the value is N+1. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 170 / 812...

  • Page 171: Audio Codec

     Stereo headphone amplifier that can be operated in capless headphone mode  Support Virtual Ground to automatic change to True Ground to protect headphone amplifier and make function work normal mode A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 171 / 812...

  • Page 172: Audio Codec Block Diagram

    Module Name Base Address 0x01C22C00 Register Name Offset Description AC_DAC_DPC 0x00 DAC Digital Part Control Register AC_DAC_FIFOC 0x04 DAC FIFO Control Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 172 / 812...

  • Page 173: Audio Codec Register Description

    0: Disable 1: Enable 30:29 MODQU. Internal DAC Quantization Levels 28:25 Levels=[7*(21+MODQU[3:0])]/128 Default levels=7*21/128=1.15 DWA. DWA Function Disable 0: Enable 1: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 173 / 812...
  • Page 174 0: 64-Tap FIR 1: 32-Tap FIR SEND_LASAT. Audio sample select when TX FIFO under run 0: Sending zero 1: Sending last audio sample A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 174 / 812...
  • Page 175 1: mono, 128 levels FIFO When enabled, L & R channel send same data TX_SAMPLE_BITS. Transmitting Audio Sample Resolution 0: 16 bits 1: 24 bits A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 175 / 812...
  • Page 176 1: More than one room for new sample in TX FIFO (>= 1 word) TXE_CNT. 22:8 0x80 TX FIFO Empty Space Word Counter TXE_INT. TX FIFO Empty Pending Interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 176 / 812...
  • Page 177 1.13.4.5. DAC ANALOG CONTROL REGISTER Offset:0x10 Register Name: AC_DAC_ACTRL Default Description DACAREN. Internal DAC Analog Right channel Enable 0:Disable 1:Enable DACALEN. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 177 / 812...
  • Page 178 When LNRDF is 1, right select LINEINL-LINEINR LFMS. Left FM to left output mixer mute 0:mute 1:Not mute RFMS. right FM to right output mixer mute 0:mute A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 178 / 812...
  • Page 179 MIC2 to output mixer right channel mute 0: mute 1: Not mute DACPAS. DAC to PA Mute 0-Mute 1-Not mute MIXPAS. Output Mixer to PA mute A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 179 / 812...
  • Page 180 31:29 110: Reserved 001: 32KHz 011: 16KHz 101: 8KHz 111: Reserved EN_AD. ADC Digital Part Enable, en_ad 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 180 / 812...
  • Page 181 Receiving Audio Sample Resolution 0: 16 bits 1: 24 bits ADC_DRQ_EN. ADC FIFO Data Available DRQ Enable. 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 181 / 812...
  • Page 182 0: No Pending IRQ 1: Data Available Pending IRQ Write ‘1’ to clear this interrupt or automatic clear if interrupt condition fails. RXO_INT. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 182 / 812...
  • Page 183 ADC Right Channel Enable 0-Disable 1-Enable ADCLEN. ADC Left Channel Enable 0-Disable 1-Enable PREG1EN. MIC1 pre-amplifier Enable 0-Disable 1-Enable PREG2EN. MIC2 pre-amplifier Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 183 / 812...
  • Page 184 0: Line-in right channel which is independent of line-in left channel 1: negative input of line-in left channel for fully differential application 15:13 LNPREG. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 184 / 812...
  • Page 185 PA Enable 0-disable 1-enable DDE. Headphone direct-drive enable, (DDE): 0-disable 1-enable COMPTEN. HPCOM output protection enable 0: protection disable 1: protection enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 185 / 812...
  • Page 186 Notes: It is used for Audio/ Video Synchronization A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 186 / 812...
  • Page 187 MIC1 pre-amplifier Gain Control 000: 0dB 001: 24dB 010: 27dB 31:29 011: 30dB 100: 33dB 101: 36dB 110: 39dB 111: 42dB A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 187 / 812...
  • Page 188 PHONEOUTS2. MIC2 Boost stage to Phone out mute 0: Mute 1: Not mute PHONEOUTS1. Right Output mixer to Phone out mute A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 188 / 812...
  • Page 189 Register Name: AC_MIC_PHONE_CAL Default Description 0: Mute 1: Not mute PHONEOUTS0 Left Output mixer to Phone out mute 0: Mute 1: Not mute A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 189 / 812...

  • Page 190: Lradc

     Support Hold Key and General Key  Support Single Key and Continue key mode  6-bit resolution  Support voltage input range from 0V to 2V A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 190 / 812...

  • Page 191: Lradc Block Diagram

    1.14.3. LRADC Register List Module Name Base Address LRADC 0x01C22800 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 191 / 812...

  • Page 192: Lradc Register Description

    Continue Mode time select, one of 8*(N+1) sample as a valuable sample data 15:14 KEY_MODE_SELECT. Key Mode Select: 13:12 00: Normal Mode 01: Single Mode 10: Continue Mode 11:8 LEVELA_B_CNT. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 192 / 812...
  • Page 193 LRADC INTERRUPT CONTROL REGISTER Offset: 0x04 Register Name: LRADC_INTC Description Read/ Default/He Write 31:16 ADC1_KEYUP_IRQ_EN. ADC 1 Key Up IRQ Enable 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 193 / 812...
  • Page 194 ADC 0 Hold Key IRQ Enable 0: Disable 1: Enable ADC0_KEYDOWN_EN ADC 0 Key Down Enable 0: Disable 1: Enable ADC0_DATA_IRQ_EN. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 194 / 812...
  • Page 195 1: IRQ Pending Notes: Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable. ADC1_KEYDOWN_IRQ_PENDING. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 195 / 812...
  • Page 196 0: NO IRQ 1: IRQ Pending Notes: Writing 1 to the bit will clear it and its corresponding A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 196 / 812...
  • Page 197 LRADC 0 Data 1.14.4.5. LRADC DATA 1 REGISTER Offset: 0x10 Register Name: LRADC_DATA Read/ Default/He Description Write 31:6 LRADC1_DATA. LRADC 1 Data A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 197 / 812...

  • Page 198: Overview

     TACQ up to 262ms  Median and averaging filter to reduce noise  Pen down detection, with programmable sensitivity  Support X, Y change A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 198 / 812...

  • Page 199: Typical Application Circuit

    M=6, and the FS_TIME must be no less than 6*(64 + 3.25) us. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 199 / 812...
  • Page 200 Y2-DATA X2-DATA FS_TIME Dual Touch No Pressure Measurement Conversion Time X1-DATA Y1-DATA Z2-DATA Z1-DATA FS_TIME Single Touch and Pressure Measurement Mode A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 200 / 812...

  • Page 201: Principle Of Operation

    3V reference source as the ADC reference voltage, application of the principle of single-ended mode is shown below: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 201 / 812...
  • Page 202 VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the ADC measurement. Y coordinate measurements are similar to X A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 202 / 812...
  • Page 203 Y plates is measured, provide a good indication of the size of the depressed area and the applied pressure. The area of the touch spot t is proportional to the size of the object touching it. And the A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 203 / 812...
  • Page 204 X-, Y-, and Z-position, the X+ input is disconnected from the pen down IRQ pull-down transistor to eliminate any pull-up resistor leakage current from flowing through the touch screen, thus causing no errors. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 204 / 812...
  • Page 205 Median Filter Size In this example, the TP_CTRL3 register bit 1 and bit 0 is configured as 2’b11. So the median filter has A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 205 / 812...

  • Page 206: Tp Register List

    Median and averaging filter Controller Register TP_INT_FIFOC 0x10 TP Interrupt FIFO Control Register TP_INT_FIFOS 0x14 TP Interrupt FIFO Status Register TP_TPR 0x18 TP Temperature Period Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 206 / 812...

  • Page 207: Tp Register Description

    ADC Clock Source Select: 0: HOSC(24MHZ) 1: Audio PLL ADC_CLK_DIVIDER. ADC Clock Divider(CLK_IN) 00: CLK/2 21:20 01: CLK/3 10: CLK/6 11: CLK/1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 207 / 812...
  • Page 208 Stylus Up De-bounce Function Select 0: Disable 1: Enable CHOP_TEMP_EN Chop temperature calibration enable 0: Disable 1: Enable TOUCH_PAN_CALI_EN. Touch Panel Calibration A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 208 / 812...
  • Page 209 Register Name: TP_CNT2 Description Read/ Default/H Write TP_SENSITIVE_ADJUST. Internal Pull-up Resistor Control 0000 least sensitive 31:28 0011 …… 1111 most sensitive A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 209 / 812...
  • Page 210 MEDIAN AND AVERAGING FILTER CONTROL REGISTER Offset: 0x0c Register Name: TP_CTRL3 Description Read/ Default/ Write 31:3 FILTER_EN. Filter Enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 210 / 812...
  • Page 211 Interrupt and DMA request trigger level for TP or Auxiliary ADC Trigger Level = TXTL + 1 TP_DATA_DRQ_EN. TP FIFO Data Available DRQ Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 211 / 812...
  • Page 212 0: No Pending IRQ 1: FIFO Overrun Pending IRQ Write ‘1’ to clear this interrupt or automatic clear if interrupt condition fails A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 212 / 812...
  • Page 213 TP TEMPERATURE PERIOD REGISTER Offset: 0x18 Register Name: TP_TPR Description Read/ Default/ Write 31:16 TEMP_EN. Temperature enable TEMP_PER. 15:0 Temperature Period A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 213 / 812...
  • Page 214 Read/ Default/H Description Write 31:12 TP_DATA. 11:0 Touch Panel X ,Ydata or Auxiliary analog input data converted by the internal ADC A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 214 / 812...
  • Page 215 100: / 101:/ 110: / 111:/ TX_P_SELECT TX_P Port Function Select: 000:Input 001:Output 010: TP_XP 011:/ 100: / 101:/ 110: / 111:/ A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 215 / 812...
  • Page 216 1.15.7.12. TP PORT DATA REGISTER Offset: 0x2c Register Name: TP_PORT_DATA Read/ Default/ Description Write 31:12 TP_PORT_DATA TP Port Data Value, TP_YN,TP_YP, TP_XN, TP_XP(y2/y1/x2/x1) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 216 / 812...

  • Page 217: Security System

     32-word RX FIFO and 32-word TX FIFO for high speed application  Support CPU mode and DMA mode  Interrupt support A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 217 / 812...

  • Page 218: Security System Block Diagram

    Security Input Key 1/ PRNG Seed 1 … … … SS_KEY7 0x20 Security Input Key 7 SS_IV0 0x24 Security Initialization Vector 0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 218 / 812...

  • Page 219: Security System Register Description

    1: Select SID_RKEYx from Security ID 2: Select SID_BKEYx from Security ID 3-10: Select internal Key n (n from 0 to 7) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 219 / 812...
  • Page 220 01: 192-bits 10: 256-bits 11: Reserved SS_OP_DIR SS Operation Direction 0: Encryption 1: Decryption SS_METHOD SS Method 000: AES 001: DES A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 220 / 812...
  • Page 221 Register Name: SS_KEY[n] Offset: 0x04 +4*n Default Value: 0x0000_0000 Read/Write Default Description SS_KEY 31:0 Key[n] Input Value (n= 0~7)/ PRNG Seed[n] (n= 0~5) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 221 / 812...
  • Page 222 0: No available data in TX FIFO 1: More than one data in TX FIFO (>= 1 word) TXFIFO_AVA_CNT 21:16 TX FIFO Available Word Counter A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 222 / 812...
  • Page 223 0: No TX FIFO pending 1: TX FIFO pending Notes: Write ‘1’ to clear or automatic clear if interrupt condition fails. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 223 / 812...
  • Page 224 SHA1/ MD5 Message digest MD[n] for SHA1/MD5 (n= 0~4) 1.16.4.8. SECURITY SYSTEM CTS LENGTH REGISTER Register Name: SS_CTS_LEN Offset: 0x60 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 224 / 812...
  • Page 225 32-bits TX FIFO for Output 1.16.4.11. SECURITY SYSTEM CLOCK REQUIREMENT Clock Name Description Requirement ahb_clk AHB bus clock >=24MHz ss_clk SS serial clock <= 150MHz A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 225 / 812...

  • Page 226: Security Jtag

    JTAG authentication function is ON. When JTAG function and JTAG authentication function is ON, the user must provide JTAG password before using JTAG function. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 226 / 812...

  • Page 227: Security Jtag Register List

    1.17.3.3. SJTAG STATUS REGISTER Register Name: SJTAG_STATUS Offset: 0x08 Default Value: 0xXXXX_XXXX Read/Write Default Description 31:1 JTAG_ONOFF_FLAG JTAG function ON/OFF flag A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 227 / 812...
  • Page 228 Register Name: SJTAG_STATUS Offset: 0x08 Default Value: 0xXXXX_XXXX Read/Write Default Description 0: JTAG function is ON 1: JTAG function is OFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 228 / 812...

  • Page 229: Security Id

     64-bit electrical fuses for securiy JTAG  16-bit electrical fuses for chip configure application  16-bit electrical fues for vendors application A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 229 / 812...

  • Page 230: Sid Block Diagram

    0x1A0 HDCP Key 0x80 Low General Key 0x2C Config & Vendor Key 0x28 SJTAG Key 0x20 Boot Key 0x10 Root Key A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 230 / 812...

  • Page 231: Port Controller

    GPIO if multiplexed functions not used. 32 external PIO interrupt sources are supported and interrupt mode can be configured by software. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 231 / 812...

  • Page 232: Port Configuration Table

    I2S1_DI Port A(PA) Multiplex Function Select Table Port B(PB) Multiplex Function Select TWI0_SCK TWI0_SDA PWM0 IR0_TX SPDIF_MCLK STANBYWFI IR0_RX I2S_MCLK AC97_MCLK A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 232 / 812...
  • Page 233 Multiplex Function Select NWE# SPI0_MOSI NALE SPI0_MISO NCLE SPI0_CLK NCE1 NCE0 NRE# NRB0 SDC2_CMD NRB1 SDC2_CLK NDQ0 SDC2_D0 NDQ1 SDC2_D1 PC10 NDQ2 SDC2_D2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 233 / 812...
  • Page 234 LCD0_D7 LVDS0_VNC LCD0_D8 LVDS0_VP3 LCD0_D9 LVDS0_VN3 PD10 LCD0_D10 LVDS1_VP0 PD11 LCD0_D11 LVDS1_VN0 PD12 LCD0_D12 LVDS1_VP1 PD13 LCD0_D13 LVDS1_VN1 PD14 LCD0_D14 LVDS1_VP2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 234 / 812...
  • Page 235 TS0_D5 CSI0_D5 PE10 TS0_D6 CSI0_D6 PE11 TS0_D7 CSI0_D7 Port E(PE) Multiplex Function Select Table Port F(PF) Multiplex Function Select SDC0_D1 JTAG_MS1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 235 / 812...
  • Page 236 UART3_RT LCD1_D2 EINT2 CSI1_D2 UART3_CT LCD1_D3 EINT3 CSI1_D3 LCD1_D4 UART4_TX EINT4 CSI1_D4 LCD1_D5 UART4_RX EINT5 CSI1_D5 LCD1_D6 UART5_TX MS_BS EINT6 CSI1_D6 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 236 / 812...
  • Page 237 KP_OUT7 SDC1_D3 CSI1_VSYNC Port H(PH) Multiplex Function Select Table Port I(PI) Multiplex Function Select TWI3_SCK TWI3_SDA TWI4_SCK PWM1 TWI4_SDA SDC3_CMD SDC3_CLK A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 237 / 812...

  • Page 238: Port Register List

    Port n Configure Register 3 (n from 0 to 8) Pn_DAT n*0x24+0x10 Port n Data Register (n from 0 to 8) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 238 / 812...

  • Page 239: Port Register Description

    111: Reserved Reserved PA6_SELECT 000: Input 001: Output 26:24 010: ETXD1 011: SPI3_CLK 100: Reserved 101: GTXD1 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 239 / 812...
  • Page 240 000: Input 001: Output 010: ERXD2 011: SPI1_CLK 100: UART2_CTS 101: GRXD2 110: Reserved 111: Reserved Reserved PA0_SELECT 000: Input 001: Output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 240 / 812...
  • Page 241 100: UART1_CTS 101: GTXCTL/ETXEN 110: Reserved 111: Reserved PA12_SELECT 000: Input 001: Output 18:16 010:EMDIO 011: UART6_TX 100: UART1_RTS 101: GMDIO A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 241 / 812...
  • Page 242 110: Reserved 111: Reserved 1.19.4.3. PA CONFIGURE REGISTER 2 Register Name: PA_CFG2 Offset: 0x08 Default Value: 0x0000_0000 Read/Write Default Description 31:7 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 242 / 812...
  • Page 243 The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 243 / 812...
  • Page 244 Read/Write Default Description PA_PULL [2i+1:2i] PA[n] Pull-up/down Select (n = 0~15) (i=0~15) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 244 / 812...
  • Page 245 110: Reserved 111: Reserved PB5_SELECT 000: Input 001: Output 22:20 010: I2S_MCLK 011: AC97_MCLK 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 245 / 812...
  • Page 246 110: Reserved 111: Reserved PB0_SELECT 000: Input 001: Output 010: TWI0_SCK 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 246 / 812...
  • Page 247 111: Reserved PB11_SELECT 000: Input 001: Output 14:12 010: I2S_DO3 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved 10:8 PB10_SELECT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 247 / 812...
  • Page 248 010: UART0_RX 011: IR1_RX 100: Reserved 101: Reserved 110: Reserved 111: Reserved PB22_SELECT 26:24 000: Input 001: Output 010: UART0_TX 011: IR1_TX A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 248 / 812...
  • Page 249 110: Reserved 111: Reserved PB17_SELECT 000: Input 001: Output 010: SPI2_MISO 011: JTAG_DI0 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 249 / 812...
  • Page 250 If the port is configured as functional pin, the undefined value will be read. 1.19.4.15. PB MULTI-DRIVING REGISTER 0 Register Name: PB_DRV0 Offset: 0x38 Default Value: 0x5555_5555 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 250 / 812...
  • Page 251 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved 1.19.4.18. PB PULL REGISTER 1 Register Name: PB_PULL1 Offset: 0x44 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 251 / 812...
  • Page 252 001: Output 22:20 010: NRE# 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved PC4_SELECT 18:16 000: Input 001: Output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 252 / 812...
  • Page 253 100: Reserved 101: Reserved 110: Reserved 111: Reserved 1.19.4.20. PC CONFIGURE REGISTER 1 Register Name: PC_CFG1 Offset: 0x4C Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 253 / 812...
  • Page 254 100: Reserved 101: Reserved 110: Reserved 111: Reserved PC10_SELECT 000: Input 001: Output 10:8 010: NDQ2 011: SDC2_D2 100: Reserved 101: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 254 / 812...
  • Page 255 110: Reserved 111: Reserved PC22_SELECT 000: Input 001: Output 26:24 010: NCE7 011: SPI2_MISO 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 255 / 812...
  • Page 256 010: NCE2 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved PC16_SELECT 000: Input 001: Output 010: NWP 011: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 256 / 812...
  • Page 257 The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 257 / 812...
  • Page 258 Default Description PC_PULL [2i+1:2i] PC[n] Pull-up/down Select (n = 0~15) 0x0000_5140 (i=0~15) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 258 / 812...
  • Page 259 110: Reserved 111: Reserved PD5_SELECT 000: Input 001: Output 22:20 010: LCD0_D5 011: LVDS0_VN2 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 259 / 812...
  • Page 260 110: Reserved 111: Reserved PD0_SELECT 000: Input 001: Output 010: LCD0_D0 011: LVDS0_VP0 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 260 / 812...
  • Page 261 111: Reserved PD11_SELECT 000: Input 001: Output 14:12 010: LCD0_D11 011: LVDS1_VN0 100: Reserved 101: Reserved 110: Reserved 111: Reserved 10:8 PD10_SELECT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 261 / 812...
  • Page 262 010: LCD0_D23 011: SMC_DET 100: Reserved 101: Reserved 110: Reserved 111: Reserved PD22_SELECT 26:24 000: Input 001: Output 010: LCD0_D22 011: SMC_VPPPP A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 262 / 812...
  • Page 263 110: Reserved 111: Reserved PD17_SELECT 000: Input 001: Output 010: LCD0_D17 011: LVDS1_VNC 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 263 / 812...
  • Page 264 000: Input 001: Output 010: LCD0_ DE 011: SMC_RST 100: Reserved 101: Reserved 110: Reserved 111: Reserved PD24_SELECT 000: Input 001: Output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 264 / 812...
  • Page 265 01: Level 1 10: Level 2 11: Level 3 1.19.4.34. PD MULTI-DRIVING REGISTER 1 Register Name: PD_DRV1 Offset: 0x84 Default Value: 0x0055_5555 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 265 / 812...
  • Page 266 00: Pull-up/down disable 01: Pull-up enable 10: Pull-down 11: Reserved 1.19.4.37. PE CONFIGURE REGISTER 0 Register Name: PE_CFG0 Offset: 0x90 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 266 / 812...
  • Page 267 100: Reserved 101: Reserved 110: Reserved 111: Reserved PE2_SELECT 000: Input 001: Output 10:8 010: TS0_SYNC 011: CSI0_HSYNC 100: Reserved 101: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 267 / 812...
  • Page 268 110: Reserved 111: Reserved PE10_SELECT 000: Input 001: Output 10:8 010: TS0_D6 011: CSI0_D6 100: Reserved 101: Reserved 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 268 / 812...
  • Page 269 Default Value: 0x0000_0000 Read/Write Default Description 31:0 1.19.4.41. PE DATA REGISTER Register Name: PE_DAT Offset: 0xA0 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 269 / 812...
  • Page 270 Offset: 0xA8 Default Value: 0x0000_0000 Read/Write Default Description 31:0 1.19.4.44. PE PULL REGISTER 0 Register Name: PE_PULL0 Offset: 0xAC Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 270 / 812...
  • Page 271 001: Output 18:16 010: SDC0_D3 011: Reserved 100: UART0_RX 101: Reserved 110: Reserved 111: Reserved PF3_SELECT 14:12 000: Input 001: Output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 271 / 812...
  • Page 272 110: Reserved 111: Reserved 1.19.4.47. PF CONFIGURE REGISTER 1 Register Name: PF_CFG1 Offset: 0xB8 Default Value: 0x0000_0000 Read/Write Default Description 31:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 272 / 812...
  • Page 273 1.19.4.51. PF MULTI-DRIVING REGISTER 0 Register Name: PF_DRV0 Offset: 0xC8 Default Value: 0x0000_0555 Read/Write Default Description 31:12 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 273 / 812...
  • Page 274 10: Pull-down 11: Reserved 1.19.4.54. PF PULL REGISTER 1 Register Name: PF_PULL1 Offset: 0xD4 Default Value: 0x0000_0000 Read/Write Default Description 31:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 274 / 812...
  • Page 275 100: SDC1_D2 101: CSI0_D8 110: Reserved 111: Reserved PG3_SELECT 000: Input 001: Output 14:12 010: TS1_DVLD 011: CSI1_VSYNC 100: SDC1_D1 101: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 275 / 812...
  • Page 276 Default Description 31:15 PG11_SELECT 000: Input 001: Output 14:12 010: TS1_D7 011: CSI1_D7 100: UART4_RX 101: CSI0_D15 110: Reserved 111: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 276 / 812...
  • Page 277 Default Value: 0x0000_0000 Read/Write Default Description 31:0 1.19.4.58. PG CONFIGURE REGISTER 3 Register Name: PG_CFG3 Offset: 0xE4 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 277 / 812...
  • Page 278 01: Level 1 10: Level 2 11: Level 3 1.19.4.61. PG MULTI-DRIVING REGISTER 1 Register Name: PG_DRV1 Offset: 0xF0 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 278 / 812...
  • Page 279 Offset: 0xFC Default Value: 0x0000_0000 Read/Write Default Description PH7_SELECT 000: Input 001: Output 30:28 010: LCD1_D7 011: Reserved 100: UART5_RX 101: MS_CLK A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 279 / 812...
  • Page 280 111: CSI1_D3 PH2_SELECT 000: Input 001: Output 10:8 010: LCD1_D2 011: Reserved 100: UART3_RTS 101: Reserved 110: EINT2 111: CSI1_D2 PH1_SELECT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 280 / 812...
  • Page 281 010: LCD1_D14 011: ETXD3 100: KP_IN4 101: SMC_VPPEN 110: EINT14 111: CSI1_D14 PH13_SELECT 22:20 000: Input 001: Output 010: LCD1_D13 011: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 281 / 812...
  • Page 282 110: EINT9 111: CSI1_D9 PH8_SELECT 000: Input 001: Output 010: LCD1_D8 011: ERXD3 100: KP_IN0 101: MS_D0 110: EINT8 111: CSI1_D8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 282 / 812...
  • Page 283 111: CSI1_D20 PH19_SELECT 000: Input 001: Output 14:12 010: LCD1_D19 011: ERXERR 100: KP_OUT1 101: SMC_SDA 110: EINT19 111: CSI1_D19 10:8 PH18_SELECT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 283 / 812...
  • Page 284 011: ETXERR 100: KP_OUT7 101: SDC1_D3 110: Reserved 111: CSI1_VSYNC Reserved PH26Select 10:8 000: Input 001: Output 010: LCD1_HSYNC 011: ECOL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 284 / 812...
  • Page 285 If the port is configured as functional pin, the undefined value will be read. 1.19.4.69. PH MULTI-DRIVING REGISTER 0 Register Name: PH_DRV0 Offset: 0x110 Default Value: 0x5555_5555 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 285 / 812...
  • Page 286 10: Pull-down 11: Reserved 1.19.4.71. PH PULL REGISTER 1 Register Name: PH_PULL1 Offset: 0x11C Default Value: 0x0000_0000 Read/Write Default Description 31:24 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 286 / 812...
  • Page 287 010: SDC3_CLK 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved PI4_SELECT 000: Input 001: Output 18:16 010: SDC3_CMD 011: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 287 / 812...
  • Page 288 101: Reserved 110: Reserved 111: Reserved 1.19.4.73. PI CONFIGURE REGISTER 1 Register Name: PI_CFG1 Offset: 0x124 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 288 / 812...
  • Page 289 001: Output 14:12 010: SPI0_CLK 011: UART5_RX 100: Reserved 101: Reserved 110: EINT23 111: Reserved PI10_SELECT 10:8 000: Input 001: Output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 289 / 812...
  • Page 290 100: HSDA 101: Reserved 110: Reserved 111: Reserved PI20_SELECT 000: Input 001: Output 18:16 010: PS2_SCK0 011: UART7_TX 100: HSCL 101: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 290 / 812...
  • Page 291 110: EINT28 111: Reserved 1.19.4.75. PI CONFIGURE REGISTER 3 Register Name: PI_CFG3 Offset: 0x12C Default Value: 0x0000_0000 Read/Write Default Description 31:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 291 / 812...
  • Page 292 Default Value: 0x0000_0555 Read/Write Default Description 31:12 Reserved PI_DRV [2i+1:2i] PI[n] Multi-Driving Select (n = 16~21) (i=0~5) 00: Level 0 01: Level 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 292 / 812...
  • Page 293 11: Reserved 1.19.4.81. PIO INTERRUPT CONFIGURE REGISTER 0 Register Name: PIO_INT_CFG0 Offset: 0x200 Default Value: 0x0000_0000 Read/Write Default Description [4i+3:4i] PIO_INT_CFG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 293 / 812...
  • Page 294 Offset: 0x208 Default Value: 0x0000_0000 Read/Write Default Description 31:24 PIO_INT_CFG [4i+3:4i] External INTn Mode (n = 16~21) (i=0~5) 0x0: Positive Edge A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 294 / 812...
  • Page 295 (n=0~21) 0: Disable 1: Enable 1.19.4.86. PIO INTERRUPT STATUS REGISTER Register Name: PIO_INT_STATUS Offset: 0x214 Default Value: 0x0000_0000 Read/Writ Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 295 / 812...
  • Page 296 Debounce Clock Pre-scale n The selected clock source is prescaled by 2^n. PIO_INT_CLK_SELECT PIO Interrupt Clock Select 0: LOSC 32Khz 1: HOSC 24Mhz A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 296 / 812...

  • Page 297: Chapter 2 Memory

    Memory Chapter 2 This chapter details the A20 memory subsystem:  DRAM  NAND FLASH A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 297 / 812...

  • Page 298: Dram

     Clock frequency can be chosen for different applications  Priority of transferring through multiple ports is programmable  Random read or write operations A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 298 / 812...

  • Page 299: Nand Flash

    Support up to 8 CE and 2 RB  Support system boot from NAND flash  Support SLC/MLC NAND and EF-NAND  Support SDR/DDR NAND interface A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 299 / 812...

  • Page 300: Nand Flash Block Diagram

    Normal Spare Batch Comman Comman Comman Control NAND Flash Basic Operation CE[7:0] CLE ALE WE RE RB[1:0] DO[7:0] DI[7:0] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 300 / 812...

  • Page 301: Nfc Timing Diagram

    Data(0) Data(n-1) EDO type Serial Access after Read Cycle (SAM1) NFC_CLE NFC_CE# NFC_WE# sample 0 NFC_RE# NFC_ALE NFC_RB# NFC_IOx Data(0) Data(n-1) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 301 / 812...
  • Page 302 NFC_CE# NFC_WE# sample NFC_RE# NFC_ALE NFC_RB# NFC_IOx Data(0) Data(n-1) Command Latch Cycle NFC_CLE NFC_CE# t5 t5 NFC_WE# NFC_RE# NFC_ALE NFC_IOx COMMAND A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 302 / 812...
  • Page 303 NFC_WE# NFC_RE# NFC_ALE NFC_IOx Addr(0) Addr(n-1) Write Data to Flash Cycle NFC_CLE NFC_CE# t6 t6 NFC_WE# NFC_RE# NFC_ALE NFC_IOx Data(0) Data(n-1) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 303 / 812...
  • Page 304 NFC_IOx d(0) d(1) d(n-1) WE# high to RE# low Timing Diagram NFC_CLE NFC_CE# NFC_WE# NFC_RE# NFC_ALE NFC_RB# NFC_IOx d(0) d(1) d(n-1) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 304 / 812...
  • Page 305 NFC_CLE setup time NFC_CLE hold time NFC_CE setup time NFC_CE hold time NFC_WE# pulse width NFC_WE# hold time NFC_ALE setup time A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 305 / 812...

  • Page 306: Nfc Operation Guide

    Loading time register(NFC_TIMING_CFG) Note: T is the clock period duration of NFC_CLK (x2). 2.2.4. NFC Operation Guide Page Read Command Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 306 / 812...
  • Page 307 Page Program Diagram EF-NAND Page Read Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 307 / 812...
  • Page 308 Interleave Page Read Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 308 / 812...

  • Page 309: Chapter 3 Graphic

    Graphic Chapter 3 This chapter mainly details the mixer processor in A20. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 309 / 812...

  • Page 310: Mixer Processor

    - Output alpha configurable support  Color key support  Scaling - 4x4 taps - 32 phase  Color space convert support A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 310 / 812...

  • Page 311: Mixer Processor Block Diagram

    Base address 0x01e80000 Register name Offset Description MP_CTL_REG Mixer control register MP_STS_REG Mixer Status register MP_IDMAGLBCTL_REG Input DMA globe control register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 311 / 812...
  • Page 312 Output address high 4bits register 0xF0 – 0xF8 MP_OUTL32ADD_REG Output address low 32bits register 0x100 – 0x108 MP_OUTLINEWIDTH_REG Output line width register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 312 / 812...

  • Page 313: Mp Register Description

    3.1.4.1. MIXER CONTROL REGISTER Offset: 0x0 Register Name: MP_CTL_REG Read/W Default/He Description rite 31:10 HWERRIRQ_EN Hardware error IRQ enable control 0:disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 313 / 812...
  • Page 314 Module working status 0:idle 1:running 11:10 HWERRIRQ_FLAG Hardware error IRQ It will be set when hardware error occur, and cleared by writing FINISHIRQ_FLAG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 314 / 812...
  • Page 315 ----Four input DMA channel use the same scan rule. ----The each output DMA channel should match the same memory scan order rule with the input DMA channel. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 315 / 812...
  • Page 316 3.1.4.5. INPUT DMA START ADDRESS LOW 32BITS REGISTER Offset: iDMA0:0x10 iDMA1:0x14 Register Name: MP_IDMA_L32ADD_REG iDMA2:0x18 iDMA3:0x1C Read/W Default/ Description rite IDMA_L32ADD 31:0 iDMA Low 32bits address in bits A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 316 / 812...
  • Page 317 The height = The value of these bits add 1 15:13 IDMA_WIDTH Memory block width in pixels 12:0 The width = The value of these bits add 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 317 / 812...
  • Page 318 31:24 Globe alpha value 23:17 IDMA_FCMODEN Fill color mode enable control 0: disable 1: enable IDMA_PS 15:12 Input data pixel sequence A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 318 / 812...
  • Page 319 8 bits input data is valid. IDMA_ROTMIRCTL Rotation and mirroring control 0:normal 3:XY 5:AX 6:AY 7:AXY Other: reserved IDMA_ALPHACTL Alpha control A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 319 / 812...
  • Page 320 0:disable input DMA channel, the respective fill-color value will stead of the input data. 1:enable 3.1.4.10. INPUT DMA FILL-COLOR REGISTER Offset: iDMA0:0x60 iDMA1:0x64 Register Name: MP_IDMAFILLCOLOR_REG iDMA2:0x68 iDMA3:0x6C A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 320 / 812...
  • Page 321 Planar YUV411 mode (UV combined only) In mode 2/3/4, following rule: ----Y component data transfer through channel 0, and UV component data transfer through channel 1. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 321 / 812...
  • Page 322 2. Planar YUV422 mode (UV combined only) Planar YUV420 mode (UV combined only) Planar YUV411 mode (UV combined only) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 322 / 812...
  • Page 323 4 taps in horizontal) 3: reserved SCA_EN Enable control Disable scaler, ignore the whole scaling setting, and the data flow will by-pass the module. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 323 / 812...
  • Page 324 = input width/output width SCA_HORFRAFCT The fractional part of the horizontal scaling ratio 15:00 the horizontal scaling ratio = input width/output width A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 324 / 812...
  • Page 325 Register Name: MP_SCAHORPHASE_REG Read/W Default/H Description rite 31:20 SCA_HORPHASE Start phase in horizontal (complement) 19:00 This value equals to start phase * 2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 325 / 812...
  • Page 326 Note: the bit is only valid in by-pass mode of Red channel ROP_GREENBYPASSSEL ROP output Green channel selection 11:10 0: channel 0 1: channel 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 326 / 812...
  • Page 327 0:pass through 1:by-pass ROP_MOD ROP type selection 0:ROP3 1:ROP4 ----In ROP3 mode, only the value of ‘channel 3 index 0 control A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 327 / 812...
  • Page 328 8:channel 0’ mix channel 1’ then sub channel 2’ in word (32bit) Other: Reserved NOD5_CTL Index 0 node5 setting ( channel 0’ and channel 1’ mix not logic ) 0:by-pass 1:not A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 328 / 812...
  • Page 329 Other: Reserved Note: the result of the add or multiply operation will select the high 8 (byte operation) or 32bits (word operation). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 329 / 812...
  • Page 330 Index 1 node4 setting ( channel 0’ and channel 1’ mix logic ) 0:and 1:or 2:xor 3:add in byte 4:add in word (32bit) 5:multiply in byte 6:multiply in word (32bit) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 330 / 812...
  • Page 331 Note: the result of the add or multiply operation will select the high 8 (byte operation) or 32bits (word operation). 3.1.4.22. ALPHA / COLOR KEY CONTROL REGISTER Offset: 0xC0 Register Name: MP_ALPHACKCTL_REG Read/W Default/ Description rite 31:11 CK_REDCON A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 331 / 812...
  • Page 332 ALPHACK_MOD Alpha / Color key mode selection 0: alpha mode 1: color key mode, using the high priority layer as matching A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 332 / 812...
  • Page 333 Green CKMIN_B Blue 3.1.4.24. COLOR KEY MAX COLOR REGISTER Offset: 0xC8 Register Name: MP_CKMAX_REG Read/W Default/ Description rite 31:24 23:16 CKMAX_R A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 333 / 812...
  • Page 334 Disable color space function, ignore the control setting, and the data flow will by-pass the module. Enable color space converting function. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 334 / 812...
  • Page 335 Note: In all YUV output data format, the CSC2 must be enabled, otherwise the output data mode will be 32bpp A8R8G8B8 mode. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 335 / 812...
  • Page 336 The value add 1 equal the actual output image width 3.1.4.29. OUTPUT ADDRESS HIGH 4BITS REGISTER Offset: 0xEC Register Name: MP_OUTH4ADD_REG Read/W Default/He Description rite 31:20 19:16 OUTCH2_H4ADD A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 336 / 812...
  • Page 337 Offset: Out channel 0:0x100 Register Name: MP_OUTLINEWIDTH_REG Out channel 1:0x104 Out channel 2:0x108 Read/W Default/He Description rite OUT_LINEWIDTH 31:0 Output channel A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 337 / 812...
  • Page 338 A1 area alpha value control 0: using A1 self pixel alpha 1: using the Output image area alpha value (bit31:24) Other: reserved A0ALPHACTL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 338 / 812...
  • Page 339 Read/W Default/He Description rite 31:29 0x4a7 CSC1_YGCOEF 28:16 0x1e6f the Y/G coefficient for CSC1 0x1cbf the value equals to coefficient*2 15:13 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 339 / 812...
  • Page 340 Register Name: MP_ICSCURCOEF_REG R/U component: 0x194 B/V component: 0x198 Read/W Default/H Description rite 31:29 0x4a7 CSC1_URCOEF 28:16 0x00 the U/R coefficient for CSC1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 340 / 812...
  • Page 341 Offset: G/Y component: 0x1A0 Register Name: MP_ICSCVBCOEF_REG R/U component: 0x1A4 B/V component: 0x1A8 Read/W Default/ Description rite 31:29 28:16 0x4a7 CSC1_VBCOEF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 341 / 812...
  • Page 342 CSC2 Y/G COEFFICIENT REGISTER Offset: G/Y component: 0x1C0 Register Name: MP_OCSCYGCOEF_REG R/U component: 0x1C4 B/V component: 0x1C8 Read/W Default/ Description rite 31:13 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 342 / 812...
  • Page 343 R/U component: 0x1D4 B/V component: 0x1D8 Read/W Default/ Description rite 31:13 CSC2_URCOEF 12:00 the U/R coefficient the value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 343 / 812...
  • Page 344 CSC2 V/B CONSTANT REGISTER Offset: 0x1EC Register Name: MP_OCSCVBCONS_REG Read/W Default/ Description rite 31:30 CSC2_VBCONS 13:00 the V/B constant the value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 344 / 812...
  • Page 345 The value equals to coefficient*2 Vertical tap1 coefficient 15:08 The value equals to coefficient*2 Vertical tap0 coefficient 07:00 The value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 345 / 812...
  • Page 346 23:16 Red value 15:08 Green value 07:00 Blue value 3.1.4.48. INPUT DATA PIXEL SEQUENCE TABLE 1-bpp mode PS=xx00 PS=xx01 PS=xx10 PS=xx11 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 346 / 812...
  • Page 347 2-bpp mode PS=xx00 PS=xx01 PS=xx10 PS=xx11 4-bpp mode PS=xx00 PS=xx01 PS=xx10 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 347 / 812...
  • Page 348 PS=xx11 8-bpp mode PS=xx00 / xx11 PS=xx01 / xx10 16-bpp @ A4R4G4B4 mode PS=0x00 PS=0x01 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 348 / 812...
  • Page 349 PS=0x10 PS=0x11 PS=1xxx, the R component is swapped with B component 16-bpp @ A1R5G5B5 mode PS=0x00 PS=0x01 PS=0x10 PS=0x11 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 349 / 812...
  • Page 350 PS=1xxx, the R component is swapped with B component 16-bpp @ interleaved YUV422 mode PS=xx00 / xx11 PS=xx01 / xx10 16-bpp @ U8V8 mode PS=xxxx A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 350 / 812...
  • Page 351 Planar YUV422 Planar YUV420 Planar YUV411 The above 3 kinds of output format are the same as input 8bpp format PS. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 351 / 812...
  • Page 352 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 352 / 812...

  • Page 353: Chapter 4 Image

    Image Chapter 4 This chapter introduces the image section of A20 processor, including:  CSI0  CSI1  TVD Here is the CMOS sensor and TV decoder with YUV data process diagram： Camera0 / TV BT601/BT656 CSI0 decoder Frame Buffer...

  • Page 354: Csi0

     Support multi-channel ITU-R BT656 time-multiplexed format  Luminance statistical value  Support 8-bit raw data input  Support 16-bit YUV422 data input A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 354 / 812...

  • Page 355: Csi0 Block Diagram

    All field 2 pixel data FIFO2 Blue pixel data Cr (V) pixel data 4.1.3.2. TIMING DIAGRAM CSI timing Vref= positive; Href= positive A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 355 / 812...
  • Page 356 16bit YUV422 Timing CCIR656 2 channel Timing A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 356 / 812...
  • Page 357 For compatibility with an 8-bit interface, CS D[1] and CS D[0] are not defined. Decode Field 1 start of active video (SAV) Field 1 end of active video (EAV) Field 1 SAV (digital blanking) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 357 / 812...

  • Page 358: Csi0 Register List

    CSI scale register CSI0_C0_F0_BUFA_REG 0X010 CSI Channel_0 FIFO 0 output buffer-A address register CSI0_C0_F0_BUFB_REG 0X014 CSI Channel_0 FIFO 0 output buffer-B address register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 358 / 812...
  • Page 359 CSI Channel_2 FIFO 1 output buffer-B address register CSI0_C2_F2_BUFA_REG 0X220 CSI Channel_2 FIFO 2 output buffer-A address register CSI0_C2_F2_BUFB_REG 0X224 CSI Channel_2 FIFO 2 output buffer-B address register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 359 / 812...

  • Page 360: Csi0 Register Description

    CSI Channel_3 line buffer length register 4.1.5. CSI0 Register Description 4.1.5.1. CSI ENABLE REGISTER Offset: 0x0000 Register Name: CSI0_EN_REG Read/ Default/He Description Write 31:1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 360 / 812...
  • Page 361 010: CCIR656(one channel) 22:20 011: YUV422 100: YUV422 16bit data bus 101: two channel CCIR656 110: reserved 111: four channel CCIR656 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 361 / 812...
  • Page 362 Field selection. Applies to CCIR656 interface only. 11:10 00: start capturing with field 1. 01: start capturing with field 2. 10: start capturing with either field. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 362 / 812...
  • Page 363 FIFO. 1: Enable video capture The CSI starts capturing image data at the start of the next frame. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 363 / 812...
  • Page 364 4.1.5.5. CSI CHANNEL_0 FIFO 0 OUTPUT BUFFER-A ADDRESS REGISTER Offset Address: 0X0010 Register Name: CSI0_C0_F0_BUFA_REG Read/W Default/ Description rite C0F0_BUFA 31:00 FIFO 0 output buffer-A address A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 364 / 812...
  • Page 365 31:00 FIFO 2 output buffer-A address 4.1.5.10. CSI CHANNEL_0 FIFO 2 OUTPUT BUFFER-B ADDRESS REGISTER Offset Address: 0X0024 Register Name: CSI0_C0_F2_BUFB_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 365 / 812...
  • Page 366 LUM_STATIS luminance statistical value 31:08 When frame done interrupt flag come, value is ready and will last until next frame done. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 366 / 812...
  • Page 367 HB_OF_INT_EN Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank. PRTC_ERR_INT_EN FIFO2_OF_INT_EN FIFO 2 overflow A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 367 / 812...
  • Page 368 CSI CHANNEL_0 INTERRUPT STATUS REGISTER Offset Address: 0X0034 Register Name: CSI0_C0_INT_STA_REG Read/W Default/ Description rite 31:08 VS_PD vsync flag HB_OF_PD Hblank FIFO overflow PRTC_ERR_PD A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 368 / 812...
  • Page 369 Horizontal pixel clock start.Pixel data is valid from this clock. 4.1.5.16. CSI CHANNEL_0 VERTICAL SIZE REGISTER Offset Address: 0X0044 Register Name: CSI0_C0_VSIZE_REG Read/W Default/ Description rite A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 369 / 812...
  • Page 370 CSI CHANNEL_1 FIFO 0 OUTPUT BUFFER-B ADDRESS REGISTER Offset Address: 0X0114 Register Name: CSI0_C1_F0_BUFB_REG Read/W Default/ Description rite C1F0_BUFB 31:00 FIFO 0 output buffer-B address A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 370 / 812...
  • Page 371 C1F2_BUFB 31:00 FIFO 2 output buffer-B address 4.1.5.24. CSI CHANNEL_1 OUTPUT BUFFER CONTROL REGISTER Offset Address: 0X0128 Register Name: CSI0_C1_BUF_CTL_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 371 / 812...
  • Page 372 When software disables video capture, it clears itself after the last pixel of the current frame is captured. SCAP_STA Still capture in progress A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 372 / 812...
  • Page 373 Indicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 373 / 812...
  • Page 374 Hblank FIFO overflow PRTC_ERR_PD FIFO2_OF_PD FIFO 2 overflow FIFO1_OF_PD FIFO 1 overflow FIFO0_OF_PD FIFO 0 overflow FD_PD Frame done CD_PD Capture done A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 374 / 812...
  • Page 375 Description rite 31:13 BUF_LEN 12:00 Buffer length of a line. Unit is byte. It is the max of the 3 FIFOs A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 375 / 812...
  • Page 376 CSI CHANNEL_2 FIFO 1 OUTPUT BUFFER-B ADDRESS REGISTER Offset Address: 0X021C Register Name: CSI0_C2_F1_BUFB_REG Read/W Default/ Description rite C2F1_BUFB 31:00 FIFO 1 output buffer-B address A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 376 / 812...
  • Page 377 1: Selected output buffer-B Double buffer mode enable 0: disable 1: enable If the double buffer mode is disabled, the buffer-A will be always A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 377 / 812...
  • Page 378 4.1.5.39. CSI CHANNEL_2 INTERRUPT ENABLE REGISTER Offset Address: 0X0230 Register Name: CSI0_C2_INT_EN_REG Read/W Default/H Description rite A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 378 / 812...
  • Page 379 For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 379 / 812...
  • Page 380 Frame done CD_PD Capture done 4.1.5.41. CSI CHANNEL_2 HORIZONTAL SIZE REGISTER Offset Address: 0X0240 Register Name: CSI0_C2_HSIZE_REG Read/ Default/He Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 380 / 812...
  • Page 381 Buffer length of a line. Unit is byte. It is the max of the 3 FIFOs 4.1.5.44. CSI CHANNEL_3 FIFO 0 OUTPUT BUFFER-A ADDRESS REGISTER Offset Address: 0X0310 Register Name: CSI0_C3_F0_BUFA_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 381 / 812...
  • Page 382 31:00 FIFO 1 output buffer-B address 4.1.5.48. CSI CHANNEL_3 FIFO 2 OUTPUT BUFFER-A ADDRESS REGISTER Offset Address: 0X0320 Register Name: CSI0_C3_F2_BUFA_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 382 / 812...
  • Page 383 Double buffer mode enable 0: disable 1: enable If the double buffer mode is disabled, the buffer-A will be always selected by CSI module. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 383 / 812...
  • Page 384 The bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, change the buffer address could only effect next frame HB_OF_INT_EN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 384 / 812...
  • Page 385 4.1.5.53. CSI CHANNEL_3 INTERRUPT STATUS REGISTER Offset Address: 0X0334 Register Name: CSI0_C3_INT_STA_REG Read/W Default/ Description rite 31:08 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 385 / 812...
  • Page 386 Horizontal pixel clock length. Valid pixel clocks of a line. 15:13 HOR_START 12:00 Horizontal pixel clock start.Pixel data is valid from this clock. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 386 / 812...
  • Page 387 Description rite 31:13 BUF_LEN 12:00 Buffer length of a line. Unit is byte. It is the max of the 3 FIFOs A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 387 / 812...

  • Page 388: Csi1

     Luminance statistical value  Support 10-bit raw data input  Support 24-bit RGB/YUV 444 input, interlace/progressive mode, pixel clock up to 148.5(1080p) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 388 / 812...

  • Page 389: Csi1 Block Diagram

    Cb (U) pixel data All field 2 pixel data FIFO2 Blue pixel data Cr (V) pixel data 4.2.4. CSI1 Timing Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 389 / 812...

  • Page 390: Csi1 Register List

    CSI FIFO 0 output buffer-A address register CSI1_F0_BUFB_REG 0X014 CSI FIFO 0 output buffer-B address register CSI1_F1_BUFA_REG 0X018 CSI FIFO 1 output buffer-A address register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 390 / 812...

  • Page 391: Csi1 Register Description

    Register Name: CSI1_EN_REG Read/ Default/He Description Write 31:1 PCLK_CNT Pclk count per frame LUMA_EN Luma enable NON16_ADD Non-16 add 0x00 RD_FIFO_EN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 391 / 812...
  • Page 392 000: RAW stream 001: reserved 22:20 010: CCIR656(one channel) 011: YUV422 100: YUV444({R, B, G} or {Pr, Pb, Y}) others: reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 392 / 812...
  • Page 393 1100: field planar YUV 444 1101: field planar YUV 422 UV combined 1110: frame planar YUV 444 1111: frame planar YUV 422 UV combined A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 393 / 812...
  • Page 394 This register is not applied to CCIR656 interface. HERF_POL Href polarity 0: negative 1: positive This register is not applied to CCIR656 interface. CLK_POL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 394 / 812...
  • Page 395 This bit is self clearing and always reads as a 0. 4.2.6.4. CSI HORIZONTAL SCALE REGISTER Offset Address: 0X000C Register Name: CSI0_SCALE_REG Read/W Default/ Description rite 31:28 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 395 / 812...
  • Page 396 31:00 FIFO 0 output buffer-B address 4.2.6.7. CSI CHANNEL_0 FIFO 1 OUTPUT BUFFER-A ADDRESS REGISTER Offset Address: 0X0018 Register Name: CSI1_F1_BUFA_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 396 / 812...
  • Page 397 CSI CHANNEL_0 FIFO 2 OUTPUT BUFFER-B ADDRESS REGISTER Offset Address: 0X0024 Register Name: CSI1_F2_BUFB_REG Read/W Default/ Description rite F2_BUFB 31:00 FIFO 2 output buffer-B address A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 397 / 812...
  • Page 398 Indicates the CSI is capturing video image data (multiple frames). The bit is set at the start of the first frame after enabling A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 398 / 812...
  • Page 399 The bit is set when the FIFO 2 become overflow. FIFO1_OF_INT_EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 399 / 812...
  • Page 400 Offset Address: 0X0034 Register Name: CSI1_INT_STA_REG Read/W Default/ Description rite 31:08 VS_PD vsync flag HB_OF_PD Hblank FIFO overflow PRTC_ERR_PD FIFO2_OF_PD FIFO 2 overflow A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 400 / 812...
  • Page 401 Horizontal pixel clock start.Pixel data is valid from this clock. 4.2.6.16. CSI CHANNEL_0 VERTICAL SIZE REGISTER Offset Address: 0X0044 Register Name: CSI1_VSIZE_REG Read/W Default/ Description rite A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 401 / 812...
  • Page 402 Description rite 31:13 BUF_LEN 12:00 Buffer length of a line. Unit is byte. It is the max of the 3 FIFOs A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 402 / 812...

  • Page 403: Tv Decoder

     All variations of analog PAL/NTSC standard supported  CVBS, 480i, 576i, 480p, 576p supported  4-channel CVBS input with 1-channel 3D filter A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 403 / 812...

  • Page 404: Chapter 5 Display

    Display Chapter 5 This chapter provides a detailed description of the display feature of A20 processor from following aspects:  TCON  HDMI  DISPLAY ENGINE FRONTEND  DISPLAY ENGINE BACKEND  TVE Here is the application block diagram of display module: A20 User Manual (Revision 1.2)
  • Page 405 DEFE0 TCON DEBE0 Video0 HDMI/ DEFE1 DEBE1 DUAL DISPLAY Video0 DEFE0 DEBE0 TCON SINGLE DISPLAY A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 405 / 812...

  • Page 406: Tcon

     Support i80 interface with 18/16/9/8 bits, up to 1280x720@60fps  Dither function for RGB666/RGB565/RGB888  Gamma correction with R/G/B channel independence A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 406 / 812...

  • Page 407: Tcon Block Diagram

    CPU TIMING Channel FIFO BASIC Flag TIMING & TTL TIMING GENERATOR CLOCK LVDS TIMING OUT1 Gamma TV TIMING Async FIFO2 GENERATOR Channel A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 407 / 812...

  • Page 408: Tcon Register List

    TCON0 ttl timing register4 TCON0_LVDS_IF_REG 0x0084 TCON0 lvds panel interface register TCON0_IO_POL_REG 0x0088 TCON0 IO polarity register TCON0_IO_TRI_REG 0x008C TCON0 IO control register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 408 / 812...
  • Page 409 TCON1_FILL_BEG1_REG 0x0310 TCON1 fill data begin register1 TCON1_FILL_END1_REG 0x0314 TCON1 fill data end register1 TCON1_FILL_DATA1_REG 0x0318 TCON1 fill data value register1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 409 / 812...

  • Page 410: Tcon Register Description

    Note: this bit determined which IO_INV/IO_TRI are valid 5.1.4.2. TCON GLOBAL INTERRUPT REGISTER0 Offset: 0x004 Register Name: TCON_GINT0_REG Read/ Default/ Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 410 / 812...
  • Page 411 SY1 match the current TCON1 scan line Write 0 to clear it. 11:0 5.1.4.3. TCON GLOBAL INTERRUPT REGISTER1 Offset: 0x008 Register Name: TCON_GINT1_REG Read/ Default/ Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 411 / 812...
  • Page 412 1: 5bit frm output TCON0_Frm_Mode_G 0: 6bit frm output 1: 5bit frm output TCON0_Frm_Mode_B 0: 6bit frm output 1: 5bit frm output A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 412 / 812...
  • Page 413 5.1.4.6. TCON0 BASIC TIMING REGISTER0 Offset: 0x048 Register Name: TCON0_BASIC0_REG Read/ Default/ Description Write 31:27 TCON0_X 26:16 Panel width is X+1 15:11 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 413 / 812...
  • Page 414 Register Name: TCON0_BASIC2_REG Read/ Default/ Description Write 31:28 27:16 TVT = (VT)/2 * Thsync Note: VT/2 >= (VBP+1 ) + (Y+1) +2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 414 / 812...
  • Page 415 0: 24bit parallel mode 1: 8bit serial mode Serial_Mode 0: 8bit/3cycle RGB serial mode(RGB888) 1: 8bit/2cycle YUV serial mode(CCIR656) 29:28 RGB888_SM0 27:26 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 415 / 812...
  • Page 416 TCON0 CPU PANEL INTERFACE REGISTER Offset: 0x060 Register Name: TCON0_CPU_IF_REG Read/ Default/ Description Write CPU_MOD 31:29 000: 18bit/256K mode 001: 16bit mode0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 416 / 812...
  • Page 417 0:read operation is finishing 1:read operation is pending 21:0 5.1.4.12. TCON0 CPU PANEL WRITE DATA REGISTER Offset: 0x064 Register Name: TCON0_CPU_WR_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 417 / 812...
  • Page 418 STV high plus width (in dclk) 31:20 Tstvh = (STVH +1) * Tdclk Note: STV has a period of one frame A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 418 / 812...
  • Page 419 OEVT 31:30 OEV period (in line) Toevt = (OEVT +1) * Thsync 29:20 OEVH 19:10 OEV high plus width (in dclk) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 419 / 812...
  • Page 420 Tldd = OEHD * Tdclk 5.1.4.19. TCON0 TTL PANEL TIMING REGISTER3 Offset: 0x080 Register Name: TCON0_TTL4_REG Read/ Default/ Description Write 31:24 Output_Data_Rate A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 420 / 812...
  • Page 421 2. When REV_SEL is 1, REV has a 2 Frame period with 50% duty. 3. Make sure REV has different polarity at the beginning of every frame(take VSYNC as reference). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 421 / 812...
  • Page 422 Write 31:30 DCLK_Sel 00: used DCLK0(normal phase offset) 29:28 01: used DCLK1(1/3 phase offset) 10: used DCLK2(2/3 phase offset) 11: reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 422 / 812...
  • Page 423 Register Name: TCON0_IO_TRI_REG Read/ Default/H Description Write 31:28 IO3_Output_Tri_En 1: disable 0: enable IO2_Output_Tri_En 1: disable 0: enable IO1_Output_Tri_En 1: disable 0: enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 423 / 812...
  • Page 424 Start_Delay This is for DE1 and DE2 TCON1_Src_Sel 00: DE CH1(FIFO2 enable) 01: DE CH2(FIFO2 enable) 1x: BLUE data(FIFO2 disable, RGB=0000FF) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 424 / 812...
  • Page 425 5.1.4.26. TCON1 BASIC TIMING REGISTER2 Offset: 0x09C Register Name: TCON1_BASIC2_REG Read/ Default/ Description Write 31:28 TCON1_XO 27:16 width is TCON1_XO+1 15:12 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 425 / 812...
  • Page 426 (in HD line) Tvt = VT/2 * Th 15:12 11:0 horizontal back porch (in HD line) Tvbp = (VBP +1) * Th A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 426 / 812...
  • Page 427 1: invert IO2 Inv 0: not invert 1: invert IO1_Inv 0: not invert 1: invert IO0_Inv 0: not invert 1: invert A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 427 / 812...
  • Page 428 23:0 0xFFFFFF 1s: disable 0s: enable 5.1.4.32. TCON CEU CONTROL REGISTER Offset: 0x100 Register Name: TCON_CEU_CTL_REG Read/ Default/H Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 428 / 812...
  • Page 429 Description Write 31:13 Coef_Value 12:0 signed 13bit value, range of (-16,16) Offset: 0x11c Register Name: TCON_CEU_ADD_RC_REG Read/ Default/ Description Write 31:19 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 429 / 812...
  • Page 430 Register Name: TCON_CEU_ADD_GC_REG Read/ Default/ Description Write 31:19 Coef_Value 18:0 signed 19bit value, range of (-16384, 16384) Offset: 0x130 Register Name: TCON_CEU_MUL_BR_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 430 / 812...
  • Page 431 19bit value, range of (-16384, 16384) Offset: 0x140 Register Name: TCON_CEU_RANGE_R_REG Read/ Default/ Description Write 31:24 Coef_Range_Min 23:16 unsigned 8bit value, range of [0,255] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 431 / 812...
  • Page 432 8bit value, range of [0,255] 5.1.4.34. TCON1 FILL DATA CONTROL REGISTER Offset: 0x300 Register Name: TCON1_FILL_CTL_REG Read/ Default/ Description Write TCON1_Fill_En: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 432 / 812...
  • Page 433 31:24 23:0 Fill_End 5.1.4.37. TCON1 FILL DATA VALUE REGISTER Offset: 0x30C Register Name: TCON1_FILL_DATA0_REG Read/ Default/ Description Write 31:24 23:0 Fill_Value A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 433 / 812...
  • Page 434 31:24 23:0 Fill_Value 5.1.4.41. TCON1 FILL DATA BEGIN REGISTER Offset: 0x31C Register Name: TCON1_FILL_BEG2_REG Read/ Default/ Description Write 31:24 23:0 Fill_Begin A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 434 / 812...
  • Page 435 31:24 23:0 Fill_End 5.1.4.43. TCON1 FILL DATA VALUE REGISTER Offset: 0x324 Register Name: TCON1_FILL_DATA2_REG Read/ Default/H Description Write 31:24 23:0 Fill_Value A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 435 / 812...

  • Page 436: Hdmi

     Support up to 8 channels, 24-bit PCM(IEC60958)  Support IEC61937 compress audio formats  Hardware receiver active sense and hot plug detection A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 436 / 812...

  • Page 437: Hdmi Block Diagram

    Int_Status 0x008 Interrupt register 0x00c HDMI hot plug detect register VID_Ctrl 0x010 Video control register VID_Timing_0 0x014 Video timing register 0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 437 / 812...
  • Page 438 DDC Slave Address Register DDC_Int_Mask 0x508 DDC Interrupt Mask Register DDC_Int_Status 0x50C DDC Interrupt Status Register DDC_FIFO _Ctrl 0x510 DDC FIFO Control Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 438 / 812...

  • Page 439: Hdmi Register Description

    5.2.4.2. SYSTEM CONTROL REGISTER Offset: 0x004 Register name: Ctrl Read/ Default/ Description Write MODULE_EN 0:disable 1:enable HDCP_EN: 0:disable 1:reserved 29:2 reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 439 / 812...
  • Page 440 0: interrupt disable 1: interrupt enable 15:7 reserved AUD_FIFO_UNDER_FLOW Audio input fifo under flow flag R/Clea 0: normal 1: under flow happen A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 440 / 812...
  • Page 441 1: RX pull high 0: RX pull low RX_ACTIVE_SENSE(PIN TX2-) 1: RX pull high 0: RX pull low RX_ACTIVE_SENSE(PIN TX1+) 1: RX pull high A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 441 / 812...
  • Page 442 Offset: 0x010 Register name: VID_Ctrl Read Default Bits Description /Write /Hex VIDEO_EN 0:Video module disable 1:Video module operating HDMI_MODE: 0:DVI 1:HDMI A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 442 / 812...
  • Page 443 Default Bits Description /Write /Hex 31:28 reserved VID_ACT_V: 27:16 Video active vertical resolution is : VID_ACT_V+1 pixels 15:12 reserved 11:0 VID_ACT_H: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 443 / 812...
  • Page 444 VID_VFP: 27:16 Vertical front porch is: VID_VFP+1 TMDS clock 15:12 reserved VID_HFP: 11:0 Horizontal front porch is: VID_HFP+1 TMDS clock A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 444 / 812...
  • Page 445 VID_VSYNC_ACTIVE_SEL: Vsync priority selection 0: active low 1: active high VID_HSYNC_ACTIVE_SEL: Hsync priority selection 0: active low 1: active high A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 445 / 812...
  • Page 446 /Hex Audio Source DMA Mode 0: dedicated DMA 1: normal DMA 30:26 reserved DMA REQ CRTL 25:24 00: 1/2 FIFO empty A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 446 / 812...
  • Page 447 Audio data to send when FIFO is underflow 5.2.4.13. AUDIO FORMAT CONTROL REGISTER Offset: 0x048 Register name: Aud_Fmt Read Default Bits Description /Write /Hex A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 447 / 812...
  • Page 448 So the source should check the CA field of the audio info-frame to decide which channel will be output. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 448 / 812...
  • Page 449 010: 3 sample 22:20 011: 4 sample 100: 5 sample 101: 6 sample 110: 7 sample 111: 8 sample reserved 18:16 PCM_CH4_MAP: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 449 / 812...
  • Page 450 110: 7 sample 111: 8 sample reserved PCM_CH1_MAP: 000: 1 sample 001: 2 sample 010: 3 sample 011: 4 sample A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 450 / 812...
  • Page 451 Audio clock regeneration factor CTS 5.2.4.16. AUDIO N REGISTER Offset: 0x054 Register name: Aud_N Read Default Bits Description /Write /Hex 31:20 reserved 19:0 AUDIO_CLK_GEN_N A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 451 / 812...
  • Page 452 0x00 Source number CATEGORY CODE 15:8 0x00 Category code MODE 0x00 00: Default Mode 01~11: Reserved EMPHASIS 0x00 Additional format information A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 452 / 812...
  • Page 453 CGMS-A 00: Copying is permitted without restriction 0x00 01: One generation of copies may be made 10: Condition not be used A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 453 / 812...
  • Page 454 110: 17 bits 111: Reserved For bit 0 = “1”: 000: not indicated 001: 20 bits 010: 22 bits 100: 23 bits A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 454 / 812...
  • Page 455 AVI data byte 3 AVI_PB4 0x07 0x00 AVI data byte 4 AVI_PB5 0x08 0x00 AVI data byte 5 0x09 0x00 AVI_PB6 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 455 / 812...
  • Page 456 AUD_HB1 0x01 0x00 Packet version AUD_HB2 0x02 0x00 Packet length AUD_PB0 0x03 0x00 checksum AUD_PB1 0x04 0x00 AUD data byte 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 456 / 812...
  • Page 457 BYTE Description /Write /Hex 0x00 0x00 ACP_HB1 ACP_Type ACP_HB2 0x01 0x00 Reseved 0x02 0x00 ACP_PB0 0x03 0x00 ACP_PB1 0x04 0x00 ACP_PB2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 457 / 812...
  • Page 458 0x00 Packet version GCP _HB2 0x02 0x00 Packet length 0x03 0x00 GCP _PB0 0x04 0x00 GCP _PB1 0x05 0x00 GCP _PB2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 458 / 812...
  • Page 459 0x0c 0x00 USER_PB9 0x0d 0x00 USER_PB10 0x0e 0x00 USER_PB11 0x0f 0x00 USER_PB12 0x10 0x00 USER_PB13 0x11 0x00 USER_PB14 0x12 0x00 USER_PB15 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 459 / 812...
  • Page 460 Register name: Pad_Ctrl0 Read Default Bits Description /Write /Hex BIASEN LDOCEN LDODEN PWENC PWEND PWENG CKEN TXEN Autosync_dis 0: enable auto sync A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 460 / 812...
  • Page 461 /Write /Hex 31:24 reserved AMP_OPT AMPCK_OPT DMPOPT EMP_OPT EMPCK_OPT PWSCK PWSDT REG_CSMPS REG_DEN REG_DENCK REG_PLRCK 12:10 REG_EMP REG_CD REG_CKSS REG_AMP REG_PLR A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 461 / 812...
  • Page 462 PLL/DRV SETTING 3: PLL DBG0 Offset: 0x20c Register name: PLL_Dbg0 Read Default Bits Description /Write /Hex PLL_DBG_EN 30:28 PSET 27:26 CLKSTEP 25:24 PDCLKSEL S5_7 CKIN_SEL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 462 / 812...
  • Page 463 Lock_flag2 23:17 reserved Lock_flag1 15:10 reserved Error_sf Error_sfdet reserved PLL_BNSI 5.2.4.29. PLL/DRV SETTING 5: HPD/CEC Offset: 0x214 Register name: HPD_CEC A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 463 / 812...
  • Page 464 5: 32 6: 64 7: 128 Others: reserved Pkt_3_freq(frame): 0: 1 1: 2 2: 4 27:24 3: 8 4: 16 5: 32 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 464 / 812...
  • Page 465 1: gc_packet 2: avi_infoframe 3: audio_infoframe 4: audio_related 15:12 5: spd_infoframe 6: user_define(reserved) 7: acp_pkt(reserved) 8: mpeg_info(reserved) 15:arbiter table end Others: reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 465 / 812...
  • Page 466 0: NULL packet 1: gc_packet 2: avi_infoframe 3: audio_infoframe 4: audio_related 5: spd_infoframe 6: user_define(reserved) 7: acp_pkt(reserved) 8: mpeg_info(reserved) 15:arbiter table end A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 466 / 812...
  • Page 467 4: 16 5: 32 6: 64 7: 128 Others: reserved Pkt_6_freq(frame): 0: 1 1: 2 23:20 2: 4 3: 8 4: 16 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 467 / 812...
  • Page 468 Others: reserved Pkt_7: 0: NULL packet 1: gc_packet 2: avi_infoframe 11:8 3: audio_infoframe 4: audio_related 5: spd_infoframe 6: user_define(reserved) 7: acp_pkt(reserved) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 468 / 812...
  • Page 469 15:arbiter table end Others: reserved 5.2.4.32. AUDIO NORMAL DMA PORT Offset: 0x400 Register name: Aud_TX_FIFO Read Default Bits Description /Write /Hex A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 469 / 812...
  • Page 470 DDC SLAVE ADDRESS REGISTER Offset: 0x504 Register name: DDC_Slave_Addr Read Default Bits Description /Write /Hex Addr0 31:24 Segment pointer for E-DDC read operation A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 470 / 812...
  • Page 471 1 to this bit will clear it. Note: this bit can only be set when correct FIFO direction is set. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 471 / 812...
  • Page 472 This bit is set when FIFO underflow Write 1 to this bit will clear it DDC_TX FIFO_Overflow_Interrupt_Status_Bit 0: not overflow 1: overflow A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 472 / 812...
  • Page 473 When FIFO level is below this value in write mode, DMA request and FIFO request interrupt is assert if relative enable is on. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 473 / 812...
  • Page 474 5.2.4.40. DDC ACCESS DATA BYTE NUMBER Offset: 0x51C Register name: DDC_Byte_Counter Read Default Bits Description /Write /Hex 31:10 Reserved DDC_Access_Data_Byte_Number A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 474 / 812...
  • Page 475 When DDC_SCL line state control enable is set to ‘1’, the value of this bit decide the output level of DDC_SCL 0: output low level 1: output high level DDC_SDA _LineState_Control_Bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 475 / 812...
  • Page 476 The DDC output frequency is F1/10/: F1 = F0/(M+1) Foscl = F1/10 = Fin/(2^N * (M+1) *10 The source clock frequency is the f TMDS A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 476 / 812...

  • Page 477: Display Engine Frontend

     Input support from DRAM, DEBE and interface of LCD with DEBE  Support 3D format content input/output format convert/display(including HDMI) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 477 / 812...

  • Page 478: Defe Block Diagram

    DEFE_BUF_ADDR0_REG 0x0020 Register DEFE Input Channel 1 Buffer Address DEFE_BUF_ADDR1_REG 0x0024 Register DEFE Input Channel 2 Buffer Address DEFE_BUF_ADDR1_REG 0x0028 Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 478 / 812...
  • Page 479 DEFE De-interlacing Control Register DEFE_DI_DIAGINTP_REG 0x00A4 DEFE De-interlacing Diag-Interpolate Register DEFE De-interlacing Temp-Difference DEFE_DI_TEMPDIFF_REG 0x00A8 Register DEFE_DI_SAWTOOTH_REG 0x00AC DEFE De-interlaing Sawtooth Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 479 / 812...
  • Page 480 DEFE Channel 0 Vertical factor Register DEFE_CH0_HORZPHASE_R DEFE Channel 0 Horizontal Initial Phase 0x0110 Register DEFE_CH0_VERTPHASE0_R DEFE Channel 0 Vertical Initial Phase 0 0x0114 Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 480 / 812...
  • Page 481 DEFE Channel 1 Vertical Filter Coeffient 0x0700+N*4 Register N=0:31 DEFE_VPP_EN_REG 0x0A00 DEFE Video Post Process Enable Register DEFE_VPP_DCTI_REG 0x0A04 DEFE Video Post Process Digital Chroma A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 481 / 812...

  • Page 482: Defe Register Description

    5.3.4.2. DEFE_FRM_CTRL_REG Offset: 0x4 Register Name: DEFE_FRM_CTRL_REG Read/ Default/H Description Write 31:17 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 482 / 812...
  • Page 483 If DEFE write back function is enable, DEFE output to DEBE isn’t recommended. OUT_PORT_SEL DEFE output port select 00: DEBE0 01: DEBE1 other: reserved WB_EN Write back enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 483 / 812...
  • Page 484 When the new frame starts, the bit will also be self-cleared. 5.3.4.3. DEFE_BYPASS_REG Offset: 0x8 Register Name: DEFE_BYPASS_REG Read/ Default/ Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 484 / 812...
  • Page 485 0: horizontal filtered result 1: original data 5.3.4.5. DEFE_LINT_CTRL_REG Offset: 0x10 Register Name: DEFE_LINT_CTRL_REG Read/ Default/He Description Write 31:28 27:16 CURRENT_LINE FIELD_SEL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 485 / 812...
  • Page 486 DEFE frame buffer address 31:0 In tile-based type: The address is the start address of the line in the first tile used A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 486 / 812...
  • Page 487 Field loop mode 0:the last field; 1:the full frame VALID_FIELD_CNT Valid field counter bit 10:8 the valid value = this value + 1； A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 487 / 812...
  • Page 488 Register Name: DEFE_TB_OFF1_REG Read/ Default/He Description Write 31:21 X_OFFSET1 20:16 The x offset of the bottom-right point in the end tile A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 488 / 812...
  • Page 489 The y offset of the top-left point in the first tile X_OFFSET0 The x offset of the top-left point in the first tile 5.3.4.13. DEFE_LINESTRD0_REG Offset: 0x40 Register Name: DEFE_LINESTRD0_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 489 / 812...
  • Page 490 The stride length is the distance from the start of the end line in one tile to the start of the first line in next tile(here next tile is in vertical direction) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 490 / 812...
  • Page 491 000: non-tile-based planar data 001: interleaved data 10:8 010: non-tile-based UV combined data 100: tile-based planar data 110: tile-based UV combined data other: reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 491 / 812...
  • Page 492 011: YUV 4:1:1 Other: Reserved In tile-based UV combined data mode: 001: YUV 4:2:2 010: YUV 4:2:0 011: YUV 4:1:1 Other: reserved DATA_PS A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 492 / 812...
  • Page 493 Other: reserved 5.3.4.17. DEFE_WB_ADDR0_REG Offset: 0x50 Register Name: DEFE_WB_ADDR0_REG Read/ Default/H Description Write WB_ADDR 31:0 Write-back address setting for scaled data. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 493 / 812...
  • Page 494 For ARGB, when this bit is 0, the byte sequence is BGRA, and when this bit is 1, the byte sequence is ARGB; SCAN_MOD Output interlace enable 0: disable 1: enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 494 / 812...
  • Page 495 Write 31:11 REG_LOAD_EN Register ready load interrupt enable LINE_EN Line interrupt enable WB_EN Write-back end interrupt enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 495 / 812...
  • Page 496 0: valid write back 1: un-valid write back This bit is cleared through write 0 to reset/start bit in frame control A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 496 / 812...
  • Page 497 The bit will be set when frame process reset & start is set, and be cleared when frame process reset or disabled. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 497 / 812...
  • Page 498 Default/H Description Write 31:13 COEF 12:0 the Y/G coefficient the value equals to coefficient*2 5.3.4.27. DEFE_CSC_COEF03_REG Offset: 0x7C Register Name: DEFE_CSC_COEF03_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 498 / 812...
  • Page 499 12:0 the U/R coefficient the value equals to coefficient*2 5.3.4.30. DEFE_CSC_COEF12_REG Offset: 0x88 Register Name: DEFE_CSC_COEF12_REG Read/ Default/ Description Write 31:13 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 499 / 812...
  • Page 500 12:0 the V/B coefficient the value equals to coefficient*2 5.3.4.33. DEFE_CSC_COEF21_REG Offset: 0x94 Register Name: DEFE_CSC_COEF21_REG Read/ Default/ Description Write 31:13 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 500 / 812...
  • Page 501 13:00 the V/B constant the value equals to coefficient*2 5.3.4.36. DEFE_DI_CTRL_REG Offset: 0xA0 Register Name: DEFE_DI_CTRL_REG Read/ Default/ Description Write 31:26 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 501 / 812...
  • Page 502 0: de-interlacing disable 1: de-interlacing enable 5.3.4.37. DEFE_DI_DIAGINTP_REG Offset: 0xA4 Register Name: DEFE_DI_DIAGINTP_REG Read/ Default/ Description Write 31:24 Diagintp_th3 23:16 0x10 Diagintp_th2 14:8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 502 / 812...
  • Page 503 Offset: 0xAC Register Name: DEFE_DI_SAWTOOTH_REG Read/ Default/ Description Write 31:16 15:8 sawtooth_th2 0x14 Sawtooth_th1 5.3.4.40. DEFE_DI_SPATCOMP_REG Offset: 0xB0 Register Name: DEFE_DI_SPATCOMP_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 503 / 812...
  • Page 504 Register Name: DEFE_DI_PRELUMA_REG Read/ Default/ Description Write PREFRM_ADDR 31:0 Pre-frame buffer address of luma 5.3.4.43. DEFE_DI_TILEFLAG_REG Offset: 0xBC Register Name: DEFE_DI_TILEFLAG_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 504 / 812...
  • Page 505 0: disable 1: enable 5.3.4.46. DEFE_WB_LINESTRD0_REG Offset: 0xD4 Register Name: DEFE_WB_LINESTRD0_REG Read/ Default/ Description Write LINE_STRD 31:0 Ch3 write back line-stride A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 505 / 812...
  • Page 506 2: left 2nd field 3: right 2nd field 23:19 CI_OUT_MOD 3D column interleaved mode 0: CI_1 18:16 1: CI_2 2: CI_3 3: CI_4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 506 / 812...
  • Page 507 Write RIGHT_CH0_ADDR 31:0 3D mode channel 0 buffer address This address is the start address of right image in 3D mode A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 507 / 812...
  • Page 508 The y offset of the top-left point in the first tile X_OFFSET0 The x offset of the top-left point in the first tile A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 508 / 812...
  • Page 509 The x offset of the bottom-right point in the first tile 15:13 Y_OFFSET0 12:8 The y offset of the top-left point in the first tile A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 509 / 812...
  • Page 510 Write 31:29 OUT_HEIGHT 28:16 Output layer Y/G component height The output layer height = The value of these bits add 1 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 510 / 812...
  • Page 511 = input width/output width 5.3.4.59. DEFE_CH0_VERTFACT_REG Offset: 0x10C Register Name: DEFE_CH0_VERTFACT_REG Read/ Default/ Description Write 31:24 23:16 FACTOR_INT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 511 / 812...
  • Page 512 31:20 PHASE 19:0 Y/G component initial phase in vertical for top field (complement) This value equals to initial phase * 2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 512 / 812...
  • Page 513 Tap 1 offset in horizontal TAP0 0x7D Tap 0 offset in horizontal 5.3.4.64. DEFE_CH0_HORZTAP1_REG Offset: 0x124 Register Name: DEFE_CH0_HORZTAP1_REG Read/ Default/ Description Write A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 513 / 812...
  • Page 514 TAP2 22:16 Tap 2 offset in vertical TAP1 14:8 Tap 1 offset in vertical TAP0 0x7F Tap 0 offset in vertical A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 514 / 812...
  • Page 515 The output layer width = The value of these bits add 1 12:0 When line buffer result selection is horizontal filtered result, the maximum width is 2048 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 515 / 812...
  • Page 516 = input height/output height FACTOR_FRAC The fractional part of the vertical scaling ratio 15:0 the vertical scaling ratio = input height /output height A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 516 / 812...
  • Page 517 31:20 PHASE U/R component initial phase in vertical for bottom field 19:0 (complement) This value equals to initial phase * 2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 517 / 812...
  • Page 518 30:24 Tap 7 offset in horizontal TAP6 22:16 Tap 6 offset in horizontal TAP5 14:8 Tap 5 offset in horizontal TAP4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 518 / 812...
  • Page 519 Register Name: DEFE_CH0_HORZCOEF0_REGN Read/ Default/H Description Write TAP3 Horizontal tap3 coefficient 31:24 The value equals to coefficient*2 TAP2 23:16 Horizontal tap2 coefficient A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 519 / 812...
  • Page 520 The value equals to coefficient*2 TAP5 Horizontal tap5 coefficient 15:8 The value equals to coefficient*2 TAP4 Horizontal tap4 coefficient The value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 520 / 812...
  • Page 521 The value equals to coefficient*2 TAP1 15:8 Horizontal tap1 coefficient The value equals to coefficient*2 TAP0 Horizontal tap0 coefficient The value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 521 / 812...
  • Page 522 Vertical tap2 coefficient The value equals to coefficient*2 TAP1 Vertical tap1 coefficient 15:8 The value equals to coefficient*2 TAP0 Vertical tap0 coefficient A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 522 / 812...
  • Page 523 U/V path shift are in the same sign, path shift use 0: min(|U|,|V|) 1: max(|U|,|V|) UV_DIFF_SIGN_ MAX/MIN_MODE_SEL UV direction detection using max or min of |U|/|V| in different sign A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 523 / 812...
  • Page 524 01: algorithm1 10: algorithm2 11: reserved DCTI_FILTER1_SEL DCTI 1 filter algorithm selection 00: algorithm0 01: algorithm1 10: algorithm2 11: reserved DCTI_SUPHILL_EN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 524 / 812...
  • Page 525 LP high-pass filter gain(BETA) 23:21 ALPHA 20:16 LP band-pass filter2 gain(ALPHA) 15:13 12:8 LP band-pass filter1 gain(TAU) LP_EN 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 525 / 812...
  • Page 526 LP low-pass-filter gain 5.3.4.86. DEFE_VPP_WLE_REG Offset: 0xA10 Register Name: DEFE_VPP_WLE_REG Read/ Default/ Description Write 31:24 WLE_GAIN 23:16 WLE gain WLE_THR 15:8 WLE threshold A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 526 / 812...
  • Page 527 Read/ Default/H Description Write 31:24 BLE_GAIN 23:16 BLE gain BLE_THR 15:8 BLE threshold Note: MUST BE set 0~127. BLE_EN BLE enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 527 / 812...

  • Page 528: Display Engine Backend

     YUV input channel support  Vertical keystone correction  Output color correction A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 528 / 812...

  • Page 529: Display Engine Block Diagram

    0x840 – 0x84C DEBE_LAYLINEWIDTH_REG DE-layer frame buffer line width register DE-layer frame buffer low 32 bit address 0x850 – 0x85C DEBE_LAYFB_L32ADD_REG register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 529 / 812...
  • Page 530 DE backend keystone back color control DEBE_KSBKCOLOR_REG 0x984 register DEBE_KSFSTLINEWIDTH_RE DE backend keystone output first line width 0x988 setting register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 530 / 812...
  • Page 531 0x4400-0x47FF Gamma table 0x4800-0x4BFF DE-HWC pattern memory block 0x4C00-0x4FFF DE-HWC color palette table 0x5000-0x53FF Pipe0 palette table 0x5400-0x57FF Pipe1 palette table A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 531 / 812...

  • Page 532: Debe Register Description

    15:12 LAY3_EN Layer3 Enable/Disable 0: Disabled 1: Enabled LAY2_EN Layer2 Enable/Disable 0: Disabled 1: Enabled A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 532 / 812...
  • Page 533 1: start START_CTL Normal output channel Start & Reset control 0: reset 1: start DEBE_EN DE back-end enable/disable 0: disable 1: enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 533 / 812...
  • Page 534 The real display width = The value of these bits add 1 5.4.4.4. DE-LAYER SIZE REGISTER Offset: Layer 0: 0x810 Layer 1: 0x814 Register Name: DEBE_LAYSIZE_REG Layer 2: 0x818 Layer 3: 0x81C A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 534 / 812...
  • Page 535 X is left-top x coordinate of the layer on screen in pixels The X represent the two’s complement Setting the layer0-layer3 the coordinate (left-top) on screen control information A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 535 / 812...
  • Page 536 5.4.4.8. DE-LAYER FRAME BUFFER HIGH 4 BIT ADDRESS REGISTER Offset: 0x860 Register Name: DEBE_LAYFB_H4ADD_REG Read/W Default/ Description rite 31:28 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 536 / 812...
  • Page 537 When the Module registers loading auto mode disable control bit is set, the registers will be loaded by write 1 to the bit, and the bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 537 / 812...
  • Page 538 Register Name: DEBE_CKMIN_REG Read/W Default/ Description rite 31:24 CKMIN_R 23:16 Red color key min CKMIN_G 15:8 Green Green color key min CKMIN_B A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 538 / 812...
  • Page 539 Blue Match Rule 00: always match 01: always match 10: match if (Color Min=<Color<=Color Max) 11: match if (Color>Color Max or Color<Color Min) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 539 / 812...
  • Page 540 Only 2 channels pixel data can get to Alpha Blender1 at the same screen coordinate. 17:16 LAY_PIPESEL Pipe Select 0: select Pipe 0 1: select Pipe 1 14:12 LAY_PRISEL 11:10 Priority A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 540 / 812...
  • Page 541 Setting 2 or more layers YUV channel mode is illegal, programmer should confirm it. LAY_VDOEN Layer video channel selection enable control 0: disable 1: enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 541 / 812...
  • Page 542 Setting the internal frame buffer scaling factor, only valid in internal frame buffer mode 15:14 Height scale factor 00: no scaling 01: *2 10: *4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 542 / 812...
  • Page 543 Palette Mode data format In palette mode, the data of external frame buffer is regarded as pattern. 0000: 1-bpp 0001: 2-bpp 0010: 4-bpp A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 543 / 812...
  • Page 544 DE-layer attribute control register1 [01:00] = PS (pixels sequence) Mono or internal frame buffer 1-bpp or palette 1-bpp mode FBF = 0000 PS=00 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 544 / 812...
  • Page 545 PS=01 PS=10 PS=11 Mono or internal frame buffer 2-bpp or palette 2-bpp mode FBF = 0001 PS=00 PS=01 PS=10 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 545 / 812...
  • Page 546 PS=11 Mono 4-bpp or palette 4-bpp mode FBF = 0010 PS=00 PS=01 PS=10 PS=11 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 546 / 812...
  • Page 547 FBF = 0100 or 0101 or 0110 or 0111 or 1000 PS=00 PS=01 PS=10/11 Invalid Color 24-bpp or 32-bpp mode FBF = 1001 or 1010 PS=00/01 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 547 / 812...
  • Page 548 The hardware cursor is 32*32 2-bpp pattern, this value represent the start position of the cursor in X coordinate 15:6 HWC_YSIZE A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 548 / 812...
  • Page 549 Write back data format setting ARGB (little endian system) BGRA (little endian system) 11:10 WB_EFLAG Error flag 1: write back error A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 549 / 812...
  • Page 550 The bit will be cleared when the new writing-back frame start to process. 5.4.4.18. DE BACKEND WRITE BACK ADDRESS REGISTER Offset: 0x8F4 Register Name: DEBE_WBADD_REG A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 550 / 812...
  • Page 551 SPR_EN disable enable 5.4.4.21. DE-SPRITE FORMAT CONTROL REGISTER Offset: 0x908 Register Name: DEBE_SPRFMTCTL_REG Read/W Default/ Description rite 31:13 SPR_FBPS Pixel sequence A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 551 / 812...
  • Page 552 BGRA (little endian system) 8bpp palette mode: (bit8 will be set 1) The setting status of the DE-sprite format control register bit12 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 552 / 812...
  • Page 553 X coordinate 15:0 X is left-top x coordinate of the layer on screen in pixels The X represent the two’s complement A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 553 / 812...
  • Page 554 The real block width = The value of these bits add 1 SPR_NEXTID The value determine the next block ID number from 0-31 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 554 / 812...
  • Page 555 Sprite single block line width in bits 5.4.4.26. DE BACKEND INPUT YUV CHANNEL CONTROL REGISTER Offset: 0x920 Register Name: DEBE_IYUVCTL_REG Read/W Default/ Description rite A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 555 / 812...
  • Page 556 In interleaved YUV 444 data format mode: 00: AYUV 01: VUYA Other: illegal IYUV_LINNEREN linner IYUV_EN YUV channel enable control 0: disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 556 / 812...
  • Page 557 DE BACKEND YUV CHANNEL BUFFER LINE WIDTH REGISTER Offset: Channel 0 : 0x940 Register Name: DEBE_IYUVLINEWIDTH_REG Channel 1 : 0x944 Channel 2 : 0x948 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 557 / 812...
  • Page 558 R/U component: 0x954 B/V component: 0x958 Read/W Default/ Description rite 31:29 DF_YGCOEF 28:16 the Y/G coefficient for de-flicker the value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 558 / 812...
  • Page 559 DE BACKEND U/R COEFFICIENT REGISTER Offset: G/Y component: 0x960 Register Name: DEBE_URCOEF_REG R/U component: 0x964 B/V component: 0x968 Read/ Default/He Description Write 31:29 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 559 / 812...
  • Page 560 5.4.4.34. DE BACKEND V/B COEFFICIENT REGISTER Offset: G/Y component: 0x970 Register Name: DEBE_VBCOEF_REG R/U component: 0x974 B/V component: 0x978 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 560 / 812...
  • Page 561 DE BACKEND KEYSTONE CORRECTION CONTROL REGISTER Offset: 0x980 Register Name: DEBE_KSCTL_REG Read/W Default/ Description rite 31:1 KS_EN 0: disable 1: enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 561 / 812...
  • Page 562 The width = The value of these bits add 1 5.4.4.39. DE BACKEND KEYSTONE VERTICAL SCALING FACTOR REGISTER Offset: 0x98C Register Name: DEBE_KSVSCAFCT_REG Read/W Default/ Description rite A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 562 / 812...
  • Page 563 The value equals to coefficient*2 KS_HSCATAP1COEF 15:8 Horizontal tap1 coefficient The value equals to coefficient*2 KS_HSCATAP0COEF Horizontal tap0 coefficient The value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 563 / 812...
  • Page 564 5.4.4.43. DE BACKEND OUTPUT COLOR R COEFFICIENT REGISTER Offset: R component: 0x9D0 Register Name: DEBE_OCRCOEF_REG G component: 0x9D4 B component: 0x9D8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 564 / 812...
  • Page 565 G component: 0x9E4 B component: 0x9E8 Read/W Default/ Description rite 31:14 OC_GCOEF 13:0 the G coefficient the value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 565 / 812...
  • Page 566 DE BACKEND OUTPUT COLOR B CONSTANT REGISTER Offset: 0x9FC Register Name: DEBE_OCBCONS_REG Read/W Default/H Description rite 31:15 OC_BCONS 14:0 the B constant the value equals to coefficient*2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 566 / 812...
  • Page 567 0x4800-0x4BFF Read/W Default/ Description rite Hardware cursor pixel pattern 31:0 Specify the color displayed for each of the hardware cursor pixels. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 567 / 812...
  • Page 568  255 R255 G255 B255 Color255 & palette    5.4.4.51. SPRITE PALETTE TABLE Offset: DE-sprite palette SRAM block 0x4000-0x43FF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 568 / 812...
  • Page 569 PALETTE MODE Offset: Pipe0:0x5000-0x53FF Pipe palette color table SRAM block Pipe1:0x5400-0x57FF Read/W Default/ Description rite 31:24 Alpha value 23:16 Red value 15:8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 569 / 812...
  • Page 570 In internal frame buffer mode, the RAM array is used as an on-chip frame buffer, each pixel in the RAM array is used to select one of the palette 32-bit colors. 1bpp: 2bpp: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 570 / 812...
  • Page 571 Address: Pipe0:0x5000-0x53FF Pipe palette table Pipe1:0x5400-0x57FF Read/W Default/ Description rite 31:24 Alpha value 23:16 Red value 15:8 Green value Blue value A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 571 / 812...
  • Page 572 The following figure shows the RAM array used for gamma correction and the corresponding colors output. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 572 / 812...
  • Page 573 HWC Memory Block 0x4BFF 0x4C00 HWC Palette Table 0x4FFF 0x5000 PIPE0 Palette Table 0x53FF 0x5400 PIPE1 Palette Table 0x57FF 0x5800 Reserved 0xFFFF A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 573 / 812...

  • Page 574: Tv Encoder

     Support CVBS NTSC,PAL, 4-channel CVBS output  Support YPbPr 1080p60,1080p50,720p60,720p50,576p,480p,576i,480i  Support VGA up to 1920x1200@60Hz  Plug auto detection in CVBS and YpbPr A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 574 / 812...

  • Page 575: Chapter 6 Interface

    Interface Chapter 6 This section details the interfaces that provided in A20, mainly includes:  SD/MMC  TWI  SPI  UART  PS2  IR  USB DRD  USB HOST  DIGITAL AUDIO INTERFACE  AC97  EMAC ...

  • Page 576: Sd/Mmc

     Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)  Multimedia Cards (MMC – version 4.2)  JEDEC Standard – JESD84-44, Embedded Multimedia Card (eMMC) Card Product Standard A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 576 / 812...

  • Page 577: Twi

     Interrupt on address detection  Support speed up to 400Kbits/s (‘fast mode’)  Allow operation from a wide range of input clock frequencies A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 577 / 812...

  • Page 578: Twi Controller Timing Diagram

    IIC5 IIC2 6.2.3. TWI Controller Register List Module Name Base Address TWI0 0x01C2AC00 TWI1 0x01C2B000 TWI2 0x01C2B400 TWI3 0x01C2B800 TWI4 0x01C2C000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 578 / 812...

  • Page 579: Twi Register Description

    SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA0 10-bit addressing 1, 1, 1, 1, 0, SLAX[9:8] General call address enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 579 / 812...
  • Page 580 6.2.4.3. TWI DATA REGISTER Register Name: TWI_DATA Offset: 0x08 Default Value: 0x0000_0000 Read/Write Default Description 31:8 TWI_DATA Data byte for transmitting or received A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 580 / 812...
  • Page 581 TWI will first transmit the STOP condition (if in master mode) then transmit the START condition. The M_STP bit is cleared automatically: writing a ‘0’ to this A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 581 / 812...
  • Page 582 (status code F8h) when INT_FLAG is cleared. The TWI will not respond as a slave unless A_ACK is set. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 582 / 812...
  • Page 583 Read bit received, ACK transmitted 0xB8: Data byte transmitted in slave mode, ACK received 0xC0: Data byte transmitted in slave mode, ACK not received A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 583 / 812...
  • Page 584 For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11 F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz TWI SOFT RESET REGISTER Register Name: TWI_SRST Offset: 0x18 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 584 / 812...
  • Page 585 Default Value: 0x0000_003a Read/Write Default Description 31:6 SCL_STATE Current state of TWI_SCL 0 – low 1 - high SDA_STATE Current state of TWI_SDA A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 585 / 812...
  • Page 586 1-enable TWI_SDA line control mode 6.2.4.9. TWI DVFS CONTROL REGISTER Register Name: TWI_DVFSCR Offset: 0x24 Default Value: 0x0000_0000 Read/Write Default Description 31:2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 586 / 812...

  • Page 587: Twi Controller Special Requirement

    INT line and INT_FLAG to indicate a completion for the START condition and each consequent byte transfer. At each interrupt, the micro-processor needs to check the 2WIRE_STAT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 587 / 812...
  • Page 588 SCL line until the microprocessor responds to the status of previous byte transfer or START condition. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 588 / 812...

  • Page 589: Spi

     8-bit wide by 64-entry FIFO for both transmit and receive data  Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable  Support dedicated DMA A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 589 / 812...

  • Page 590: Spi Timing Diagram

    Rising, Sample SPI_SCLK (Mode 0) SPI_SCLK (Mode 2) SPI_MOSI SPI_MISO SPI_SS Sample MOSI/ MISO pin Phase 0 SPI Phase 0 Timing Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 590 / 812...

  • Page 591: Spi Register List

    SPI DMA Control register SPI_WAIT 0x18 SPI Wait Clock Counter register SPI_CCTL 0x1C SPI Clock Rate Control register SPI_BC 0x20 SPI Burst Counter register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 591 / 812...

  • Page 592: Spi Register Description

    4. 6.3.4.2. SPI TX DATA REGISTER Register Name: SPI_TXDATA Offset: 0x04 Default Value: 0x0000_0000 Read/Write Default Description TDATA 31:0 Transmit Data A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 592 / 812...
  • Page 593 When this bit is set to 1, software must manually write SPI_CTRL_REG.SS_LEVEL (bit [17]) to 1 or 0 to control the level of SS signal. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 593 / 812...
  • Page 594 BC, this bit is cleared to zero by SPI Controller. RF_RST RXFIFO Reset Write ‘1’ to reset the control portion of the receiver FIFO and A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 594 / 812...
  • Page 595 0: Phase 0 (Leading edge for sample data) 1: Phase 1 (Leading edge for setup data) MODE SPI Function Mode Select A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 595 / 812...
  • Page 596 TF_UR_INT_EN TXFIFO under run Interrupt Enable 0: Disable 1: Enable TF_OF_INT_EN TX FIFO Overflow Interrupt Enable 0: Disable 1: Enable TF_E34_INT_EN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 596 / 812...
  • Page 597 0: Disable 1: Enable RF_F34_INT_EN RXFIFO 3/4 Full Interrupt Enable 0: Disable 1: Enable RF_F14_INT_EN RX FIFO 1/4 Full Interrupt Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 597 / 812...
  • Page 598 In master mode, it indicates that all bursts specified by BC has been exchanged. In other condition, When set, this bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 598 / 812...
  • Page 599 TXFIFO Half empty This bit is set if the TXFIFO is more than half empty. Writing 1 to this bit clears it. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 599 / 812...
  • Page 600 RXFIFO Full This bit is set when the RXFIFO is full . Writing 1 to this bit clears it. 0: Not Full A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 600 / 812...
  • Page 601 TXFIFO Not Full DMA Request Enable When enable, if more than one free room for burst, DMA request is asserted, else de-asserted. 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 601 / 812...
  • Page 602 RXFIFO Ready Request Enable This bit enables/disables the RXFIFO Ready DMA Request when one or more than one words in RXFIFO 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 602 / 812...
  • Page 603 SPI devices. The max frequency is one quarter of AHB_CLK. The divide ratio is determined according to the following table using the equation: 2^(n+1). The A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 603 / 812...
  • Page 604 Write Transmit Counter 23:0 In master mode, this field specifies the burst number that should be sent to TXFIFO before automatically sending A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 604 / 812...
  • Page 605 0: 0 byte in RXFIFO 1: 1 byte in RXFIFO … … 63: 63 bytes in RXFIFO 64: 64 bytes in RXFIFO A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 605 / 812...

  • Page 606: Spi Special Requirement

    Description Requirement AHB bus clock, as the clock source of SPI AHB_CLK AHB_CLK >= 2xSPI_SCLK module SPI_CLK SPI serial input clock A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 606 / 812...

  • Page 607: Uart

     Software/ Hardware Flow Control  Programmable Transmit Holding Register Empty interrupt  Support IrDa 1.0 SIR  Interrupt support for FIFOs, Status Change A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 607 / 812...

  • Page 608: Uart Timing Diagram

    Serial IrDA. Module Name Base Address UART0 0x01C28000 UART1 0x01C28400 UART2 0x01C28800 UART3 0x01C28C00 UART4 0x01C29000 UART5 0x01C29400 UART6 0x01C29800 UART7 0x01C29C00 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 608 / 812...

  • Page 609: Uart Register Description

    Default Value: 0x0000_0000 Read/Write Default Description 31:8 Receiver Buffer Register Data byte received on the serial input port (sin) in UART mode, A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 609 / 812...
  • Page 610 FIFO is full results in the write data being lost. 6.4.4.3. UART DIVISOR LATCH LOW REGISTER Register Name: UART_DLL Offset: 0x00 Default Value: 0x0000_0000 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 610 / 812...
  • Page 611 Also, once the DLH is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 611 / 812...
  • Page 612 0: Disable 1: Enable ERBFI Enable Received Data Available Interrupt This is used to enable/disable the generation of Received A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 612 / 812...
  • Page 613 Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 613 / 812...
  • Page 614 Reading UART status 0111 Fifth detect Line Control Register register indication while the UART is busy (USR[0] is set to one). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 614 / 812...
  • Page 615 FIFO as empty. This also de-asserts the DMA TX request. It is ‘self-clearing’. It is not necessary to clear this bit. RFIFOR RCVR FIFO Reset A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 615 / 812...
  • Page 616 When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 616 / 812...
  • Page 617 The number of bit that may be selected areas follows: 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 617 / 812...
  • Page 618 Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 618 / 812...
  • Page 619 If the FIFOs are disabled, this bit is set to “1” whenever the TX Holding Register is empty and ready to accept new data and it A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 619 / 812...
  • Page 620 Break Interrupt (BI) bit (LSR[4]). 0: no framing error 1:framing error Reading the LSR clears the FE bit. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 620 / 812...
  • Page 621 This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 621 / 812...
  • Page 622 UART. 0: cts_n input is de-asserted (logic 1) 1: cts_n input is asserted (logic 0) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 622 / 812...
  • Page 623 This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 623 / 812...
  • Page 624 0: Receive FIFO not full 1: Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 624 / 812...
  • Page 625 Default Value: 0x0000_0000 Read/Write Default Description 31:7 Transmit FIFO Level This is indicates the number of data entries in the transmit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 625 / 812...
  • Page 626 CHANGE_UPDATE After the user using HALT[1] to change the baudrate or LCR configuration, write 1 to update the configuration and waiting A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 626 / 812...

  • Page 627: Uart Special Requirement

    UART0 UART Data Carrier Detect UART1_DCD This active low signal is an input indicating when Modem A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 627 / 812...
  • Page 628 SOUT and if HALT[5] is set to ‘1’, the signal is inverted after receiving from pin SIN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 628 / 812...
  • Page 629 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 629 / 812...

  • Page 630: Ps2

     Odd parity generation and checking  Register bits for override of keyboard clock and data lines  Internal clock divider for simple clock interface A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 630 / 812...

  • Page 631: Ps2 Block Diagram

    Timing for Device Transmit Data and Master Receive Data: Tckl Tckl Tckh Tckh CLOCK Td2f Tr2d DATA HOST_CLOCK HOST_DATA DEVICE_CLOCK DEVICE_DATA A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 631 / 812...
  • Page 632 Clock falling edge to data change time during host to Tf2d Tckl-5us device transfer Tc2c Host pull low Clock to Device drive Clock 15ms Tdata Time for packet to send A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 632 / 812...

  • Page 633: Ps2 Register List

    This interrupt flag is also set when error flag bit in line status register (PS2_LSTS)is set at the same time. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 633 / 812...
  • Page 634 When write, data will be write into TXFIFO, and will be transmit on to the PS2 Bus. When read, data is read out from RXFIFO, and it is received from PS2 Bus. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 634 / 812...
  • Page 635 1 – Clock Line is forced to LOW 15:9 TXDTO_IEN TX Data Timeout Interrupt Enable STOP_IEN Stop Error Interrupt Enable ACKERR_IEN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 635 / 812...
  • Page 636 Line State of DATA. Invalid before BUS_EN set. LS_CLK Line State of CLOCK. Invalid before BUS_EN set. 15:9 TX_DTO Transmit Data Timeout Timers include: A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 636 / 812...
  • Page 637 Tckl+Tckh<100us(one cycle time, as host) Note: This bit can be cleared by writing ‘1’, writing ‘0’ has no effect. 6.5.5.5. PS2 FIFO CONTROL REGISTER A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 637 / 812...
  • Page 638 RXRDY_IEN RXFIFO Ready Interrupt Enable 6.5.5.6. PS2 FIFO STATUS REGISTER Register Name: PS2_FSTS Offset: 0x0014 Default Value: 0x0000_0100 Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 638 / 812...
  • Page 639 Note: This bit can be cleared by writing ‘1’, writing ‘0’ has no effect. RX_UF RXFIFO Underflow When this bit is set, RXFIFO is underflow, and it means that A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 639 / 812...
  • Page 640 SCDF = APB_CLK/SAMPLE_CLK – 1 Frequency of sample clock is constant, and so, frequency of APB_CLK must be in the range 1-256MHz. 0x4F CLK_DIV A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 640 / 812...

  • Page 641: Ps2 Special Requirements

    PS2 clock signal PS2_DATA IN/OUT PS2 data signal 6.5.6.2. PS2 CLOCK REQUIREMENT Clock Name Description Requirement apb_clk APB bus clock >=1MHz A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 641 / 812...

  • Page 642: Overview

    IR Control Register IR_TXCTL 0x04 IR Transmitter Configure Register IR_TXADR 0x08 IR Transmitter Address Register IR_TXCNT 0x0C IR Transmitter Counter Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 642 / 812...

  • Page 643: Ir Register Description

    00: 0.576 Mbit/s MIR mode 01: 1.152 Mbit/s MIR mode 10: 4.0 Mbit/s FIR mode 11: CIR mode for Remote control or wireless keyboard A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 643 / 812...
  • Page 644 Send CRC16 and STO for MIR or CRC32 and STO for FIR 1: Send packet abort symbol Send 7’b111,1111 for MIR or 8’b0000,0000 for FIR A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 644 / 812...
  • Page 645 Transmit Packet Address This field contains the 8-bit Transmit Packet Address. If the HAG bit is cleared, the TPA bits have no effect. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 645 / 812...
  • Page 646 1: Clears the RX FIFO upon detection of illegal symbol RPPI Receiver Pulse Polarity Invert 0: Not invert receiver signal A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 646 / 812...
  • Page 647 6.6.3.7. IR RECEIVER COUNTER REGISTER Register Name: IR_RXCNT Offset: 0x18 Default Value: 0x0000_0000 Read/Write Default Description 31:12 11:0 Receiver Packet Length A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 647 / 812...
  • Page 648 Default Description 31:8 RX_DATA Receiver Byte FIFO 6.6.3.10. IR TRANSMITTER INTERRUPT CONTROL REGISTER Register Name: IR_TXINT Offset: 0x24 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 648 / 812...
  • Page 649 Transmitter Packet (the address, control and data fields) End Interrupt Enable 0: Disable 1: Enable TUI_EN Transmitter FIFO Under run Interrupt Enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 649 / 812...
  • Page 650 Transmitter Packet End 0: Transmissions of address, control and data fields not completed 1: Transmissions of address, control and data fields completed A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 650 / 812...
  • Page 651 When set to ‘1’, the Receiver FIFO IRQ is asserted if reaching RAL. The IRQ is de-asserted when condition fails. CRCI_EN Receiver CRC Error Interrupt Enable 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 651 / 812...
  • Page 652 16: 16 byte available data in RX FIFO RX FIFO Available 0: RX FIFO not available according its level 1: RX FIFO available according its level A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 652 / 812...
  • Page 653 Default Value: 0x0000_1828 Read/Write Default Description 31:25 SCS2 Bit2 of Sample Clock Select for CIR This bit is defined by SCS bits below. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 653 / 812...
  • Page 654 Sample Clock Select for CIR SCS[1 SCS[0 Sample Clock ir_clk/64 ir_clk/128 ir_clk/256 ir_clk/512 ir_clk Reserved Reserved Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 654 / 812...
  • Page 655 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 655 / 812...

  • Page 656: Usb Drd

    (Endpoint1, Endpoint2, Endpoint3, Endpoint4, Endpoint5) 6.7.2. USB DRD Timing Diagram Please refer USB2.0 Specification and its On-The-Go Supplement to the USB 2.0 Specification. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 656 / 812...

  • Page 657: Usb Host

     The USB HOST system contains two HCI controllers. The HCI controllers are composed of an EHCI controller and an OHCI companinon controller. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 657 / 812...

  • Page 658: Usb Host Block Diagram

    Please refer USB2.0 Specification and EHCI Specification V1.0. 6.8.4. USB Host Register List Module Name Base Address USB_HCI0 0x01C14000 USB_HCI1 0x01C1C000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 658 / 812...

  • Page 659: Ehci Register Description

    The value in these bits indicates an offset to add to register base to find the beginning of the Operational Register Space. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 659 / 812...
  • Page 660 This field will always fix with ‘0’. Port Routing Rules This field indicates the method used by this implementation for A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 660 / 812...
  • Page 661 PCI header defined for this calss of device. The value of this field is always ‘00b’. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 661 / 812...
  • Page 662 Reserved These bits are reserved for future use and should return a value of zero when read. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 662 / 812...
  • Page 663 The only valid values are defined below: 23:16 0x08 Valu Minimum Interrupt Interval 0x00 Reserved 0x01 1 micro-frame 0x02 2 micro-frame A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 663 / 812...
  • Page 664 Park Mode Enable is a one as it will result in undefined behavior. LHCR Light Host Controller Reset(OPTIONAL) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 664 / 812...
  • Page 665 Do not process the Asynchronous Schedule. Use the ASYNLISTADDR register to access the Asynchronous Schedule. The default value of this field is ‘0b’. Periodic Schedule Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 665 / 812...
  • Page 666 Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 666 / 812...
  • Page 667 Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 667 / 812...
  • Page 668 The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 668 / 812...
  • Page 669 The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 669 / 812...
  • Page 670 The interrupt is acknowledged by software clearing the USBERRINT bit. USB Interrupt Enable When this bit is 1, and the USBINT bit in the USBSTS register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 670 / 812...
  • Page 671 Register Name: PERIODICLISTBASE Offset: 0x24 Default Value: Undefined Read/Write Default Description BADDR 31:12 Base Address These bits correspond to memory address signals [31:12], A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 671 / 812...
  • Page 672 Bits in this field cannot be modified by system software and will always return a zero when read. Note: Write must be DWord Writes. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 672 / 812...
  • Page 673 The default value in this field is ‘0’. Wake on Connect Enable(WKCNNT_E) Writing this bit to a one enable the port to be sensitive to A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 673 / 812...
  • Page 674 Interpretation Not Low-speed device, perform EHCI reset. J-state Not Low-speed device, perform EHCI reset. K-state Low-speed device, release ownership of port. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 674 / 812...
  • Page 675 Suspend Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits[Port Enables, Port State Suspend] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 675 / 812...
  • Page 676 USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this remains a A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 676 / 812...
  • Page 677 Ports can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 677 / 812...

  • Page 678: Ohci Register List

    The Control and Status Partition Register HcRevision 0x400 HcRevision Register HcCtl 0x404 HcControl Register HcCommandStatus 0x408 HcCommandStatus Register HcInterruptStatus 0x40c HcInterruptStatus Register HcInterruptEnable 0x410 HcInterruptEnable Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 678 / 812...

  • Page 679: Ohci Register Description

    0x11 corresponds to version 1.1. All of the HC 0x10 implementations that are compliant with this specification will have a value of 0x10. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 679 / 812...
  • Page 680 When disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be removed, A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 680 / 812...
  • Page 681 These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 681 / 812...
  • Page 682 6.8.7.4. HCINTERRUPTSTATUS REGISTER Register Name: HcInterruptStatus Offset: 0x40c Default Value:0x0 Read/Write Default Description 31:7 Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 682 / 812...
  • Page 683 Enable interrupt generation due to Root Hub Status Change; FrameNumberOverflow Interrupt Enable Ignore; Enable interrupt generation due to Frame Number Over Flow; UnrecoverableError Interrupt Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 683 / 812...
  • Page 684 ResumeDetected Interrupt Disable Ignore; Disable interrupt generation due to Resume Detected; StartofFrame Interrupt Disable Ignore; Disable interrupt generation due to Start of Flame; A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 684 / 812...
  • Page 685 PCED, through bit 0 to bit 3 must be zero in this field. 6.8.7.9. HCCONTROLHEADED REGISTER Register Name: HcControlHeadED[CHED] Offset: 0x420 Default Value: 0x0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 685 / 812...
  • Page 686 Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 686 / 812...
  • Page 687 PCED, through bit 0 to bit 3 must be zero in this field. 6.8.7.14. HCFMINTERVAL REGISTER Register Name: HcFmInterval Register Offset: 0x434 Default Value:0x2edf Read/Write Default Description A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 687 / 812...
  • Page 688 FrameInterval of HcFmInterval and uses the updated value from the next SOF. 6.8.7.16. HCFMNUMBER REGISTER Register Name: HcFmNumber Offset: 0x43c Default Value:0x0 Read/Write Default Description 31:16 Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 688 / 812...
  • Page 689 Offset: 0x448 Default Value:0x02001201 Read/Write Default Description PowerOnToPowerGoodTime[POTPGT] 31:24 0x02 This byte specifies the duration HCD has to wait before accessing A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 689 / 812...
  • Page 690 These bits specify the number of downstream ports supported by the Root Hub. It is implementation-specific. The minimum number 0x01 of ports is 1. The maximum number of ports supported. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 690 / 812...
  • Page 691 This bit is set by hardware when a change has occurred to the OverCurrentIndicator field of this register. The HCD clears this bit by writing a ‘1’.Writing a ‘0’ has no effect. (read)LocalPowerStartusChange A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 691 / 812...
  • Page 692 PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 692 / 812...
  • Page 693 HCD sets this bit by writing SetPortPower or SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 693 / 812...
  • Page 694 PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 694 / 812...
  • Page 695 The CurrentConnectStatus is not affected by any write. Note: This bit is always read ‘1’ when the attached device is nonremovalble(DviceRemoveable[NumberDownstreamPort]). A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 695 / 812...

  • Page 696: Usb Host Special Requirement

    System clock (provided by AHB bus clock). This clock needs to be >30MHz. CLK60M Clock from PHY for HS SIE, is constant to be 60MHz. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 696 / 812...

  • Page 697: Digital Audio Interface

     Programmable FIFO thresholds  Interrupt and DMA support  Two 32-bit counters for AV sync application  Loopback mode for test A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 697 / 812...

  • Page 698: Digital Audio Interface Block Diagram

    TX FIFO Codec Engine 6.9.3. Digital Audio Interface Timing Diagram I2S_LRC Left Channel Right Channel I2S_SCLK I2S_SDO/SDI Standard I2S Timing Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 698 / 812...
  • Page 699 14 15 16 PCM_IN Undefined 10 11 12 13 14 15 16 Undefined PCM Short Frame SYNC Timing Diagram (16-bits sample example) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 699 / 812...

  • Page 700: Digital Audio Interface Register List

    6.9.5. Digital Audio Interface Register Description 6.9.5.1. DIGITAL AUDIO CONTROL REGISTER Register Name: DA_CTL Offset: 0x00 Default Value: 0x0000_0000 Read/Write Default Description 31:12 SDO3_EN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 700 / 812...
  • Page 701 0: I2S Interface 1: PCM Interface TXEN Transmitter Block Enable 0: Disable 1: Enable RXEN Receiver Block Enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 701 / 812...
  • Page 702 1: MSB is available on 1st BCLK rising edge after LRC rising edge BCLK Parity 0: Normal 1: Inverted Sample Resolution 00: 16-bit 01: 20-bit 10: 24-bit 11: Reserved Word Select Size A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 702 / 812...
  • Page 703 1: Suppress PCM_SYNC whilst keeping PCM_CLK running. Some Codec utilize this to enter a low power state. PCM Out Mute Write 1 force PCM_OUT to 0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 703 / 812...
  • Page 704 It should be set ‘1’ for 8 clocks width slot. RX_PDM PCM Data Mode 00: 16-bits Linear PCM 01: 8-bits Linear PCM 10: 8-bits u-law 11: 8-bits A-law A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 704 / 812...
  • Page 705 Host can get one sample by reading this register. The left channel sample data is first and then the right channel sample. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 705 / 812...
  • Page 706 Mode 1: FIFO_I[23:0] = {4’h0, TXFIFO[19:0]} RXOM RX FIFO Output Mode (Mode 0, 1, 2, 3) 00: Expanding ‘0’ at LSB of DA_RXFIFO register. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 706 / 812...
  • Page 707 RX FIFO Available 0: No available data in RX FIFO 1: More than one sample in RX FIFO (>= 1 word) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 707 / 812...
  • Page 708 0: Disable 1: Enable When set to ‘1’, RXFIFO DMA Request line is asserted if Data is available in RX FIFO. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 708 / 812...
  • Page 709 TX FIFO Empty Pending Interrupt 0: No Pending IRQ 1: FIFO Empty Pending Interrupt Write ‘1’ to clear this interrupt or automatic clear if interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 709 / 812...
  • Page 710 Notes: Whether in Slave or Master mode, when this bit is set to 1, MCLK should be output. BCLKDIV BCLK Divide Ratio from MCLK A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 710 / 812...
  • Page 711 The TX sample counter register can be set to any initial valve at any time. After A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 711 / 812...
  • Page 712 31:3 TX_CHSEL TX Channel Select 0: 1-ch 1: 2-ch 2: 3-ch 3: 4-ch 4: 5-ch 5: 6-ch 6: 7-ch 7: 8-ch A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 712 / 812...
  • Page 713 TX_CH5_MAP TX Channel5 Mapping 000: 1 sample 22:20 001: 2 sample 010: 3 sample 011: 4 sample 100: 5 sample A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 713 / 812...
  • Page 714 TX Channel2 Mapping 000: 1 sample 001: 2 sample 10:8 010: 3 sample 011: 4 sample 100: 5 sample 101: 6 sample A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 714 / 812...
  • Page 715 6.9.5.15. DIGITAL AUDIO RX CHANNEL SELECT REGISTER Register Name: DA_RXCHSEL Offset: 0x38 Default Value: 0x0000_0001 Read/Write Default Description 31:3 RX_CHSEL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 715 / 812...
  • Page 716 000: 1 sample 10:8 001: 2 sample 010: 3 sample 011: 4 sample Others: Reserved RX_CH1_MAP RX Channel1 Mapping 000: 1 sample A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 716 / 812...

  • Page 717: Digital Audio Interface Special Requirement

    32kHz, 44.1kHz, 48kHz or 96kHz. For different sampling frequencies, the tables list the coefficient value of MCLKDIV and BCLKDIV. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 717 / 812...
  • Page 718 There are two clocks for Digital Audio Interface. One is from APB bus and one is from Audio PLL. Name Description Audio_PLL 24.576Mhz or 22.528Mhz generated by Audio PLL A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 718 / 812...
  • Page 719 APB bus system clock. In I2S mode, it is requested >= 0.25 BCLK. In PCM APB_CLK mode, it is requested >= 0.5 BCLK. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 719 / 812...

  • Page 720: Ac97 Interface

     Channels support mono or stereo samples of 16(standard), 18(optional) and 20(optional) bit wide  One 96×20-bit FIFO and one 32×20-bit FIFO for data transfer  Programmable FIFO thresholds  Interrupt and DMA support A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 720 / 812...

  • Page 721: Ac97 Block Diagram

    10.2. AC97 Block diagram FSM & Control TX FIFO Engine AC-Link AC-Link RX FIFO Interrupt Control AC97 Interface Block Diagram Operation Flow Diagram A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 721 / 812...

  • Page 722: Ac97 Interface Clock Tree

    BIT_CLK, and subsequently sampled by the receiving device on the receiving side of AC-link on each immediately following falling edge of BIT_CLK. 6.10.4. AC Link Frame Format Bi-directional AC-link Frame with slot assignments A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 722 / 812...

  • Page 723: Ac97 Interface Timing Diagram

    6.10.5. AC97 Interface Timing Diagram 6.10.5.1. COLD RESET TIMING DIAGRAM Cold Reset timing parameters A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 723 / 812...
  • Page 724 6.10.5.2. WARM RESET TIMING DIAGRAM Warm Reset timing parameters 6.10.5.3. POWER DOWN TIMING DIAGRAM AC-link low power mode timing parameters A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 724 / 812...
  • Page 725 6.10.5.4. AC-LINK CLOCK BIT_CLK and SYNC Timing diagram BIT_CLK and SYNC Timing Parameters A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 725 / 812...
  • Page 726 AC-link Output Valid Delay Timing Parameters AC-link Input Setup and Hold Timing Parameters AC-link Combined Rise or Fall plus Flight Timing Parameters A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 726 / 812...

  • Page 727: Ac97 Interface Register List

    Signal rise and fall timing diagram Signal Rise and Fall Time Parameters 10.6. AC97 Interface Register List Module Name Base Address AC97 0x01C21400 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 727 / 812...

  • Page 728: Ac97 Interface Register Description

    Read/Wr Default Description 31:19 CS_RF CODEC Status Register FLAG 0: Empty 1: Full CMD_RF CMD Register FLAG 0: Empty 1: Full A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 728 / 812...
  • Page 729 A disable on this bit overrides any other block or channel enables and flushes all FIFOs. 0: Disable 1: Enable WARM_RST Warm reset A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 729 / 812...
  • Page 730 1 : DRA VRA_MODE VRA Mode 0 : Non-VRA 1 : VRA TX_RES TX Audio data resolution 00: 16-bit 01: 18-bit A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 730 / 812...
  • Page 731 0x0000 Codec command data 6.10.7.4. AC97 CODEC STATUS REGISTER Register Name: AC_CS Offset: 0x0C Default Value: 0x0000_0000 Read/Write Default Description 31:23 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 731 / 812...
  • Page 732 6.10.7.7. AC97 FIFO CONTROL REGISTER Register Name: AC_FCTL Offset: 0x18 Default Value: 0x0000_3078 Read/Write Default Description 31:18 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 732 / 812...
  • Page 733 Mode0: RXFIFO[31:0] = {FIFO_O[19:2], 14’h0} Mode 1: RXFIFO[31:0] = {14’FIFO_O[19], FIFO_O[19:2]} Mode 2: RXFIFO[31:0] = {FIFO_O[19:4], 16’h0} Mode 3: RXFIFO[31:0] = {16’FIFO_O[19], FIFO_O[19:4]} A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 733 / 812...
  • Page 734 Default Value: 0x0000_0000 Read/Write Default Description 31:10 CODEC_GPIO_EN Codec GPIO interrupt enable 0: Disable 1: Enable CREN Codec Ready interrupt enable 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 734 / 812...
  • Page 735 RXOI_EN RX FIFO Overrun Interrupt Enable 0: Disable 1: Enable RXAI_EN RX FIFO Data Available Interrupt Enable 0: Disable 1: Enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 735 / 812...
  • Page 736 Write “1” to clear this interrupt or automatically clear if interrupt condition fails. RXO_INT RX FIFO Overrun Pending Interrupt 0: FIFO Overrun Pending Write “1” to clear this interrupt A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 736 / 812...
  • Page 737 After been updated by the initial value, the counter register should count on base of this value. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 737 / 812...

  • Page 738: Ac97 Interface Special Requirement

    Clock Name Description Requirement apb_clk APB bus clock AC97 serial access x1 s_clk 24.576 MHz or 22.5792 MHz from CCU clock A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 738 / 812...

  • Page 739: Emac

     Support loop back operation  Provide MII Interface for external Ethernet PHY  3KB FIFO for TX  13KB FIFO for RX A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 739 / 812...

  • Page 740: Emac Block Diagram

    TX FIFO RX FIFO TX FIFO RX FIFO CONTROL CONTROL Regfile PACKET FRAME & FLOW FILTER CONTROL MAC CONTROL MII Interface A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 740 / 812...

  • Page 741: Emac Operation Diagram

    CPU Transmit Data DMA Operation Packet to TX FIFO TX to MAC Transmit Operation MAC Operation Retry Abort Transmit OK Transmit fail A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 741 / 812...
  • Page 742 Each received packet has 8-byte header followed with data of the reception packet which CRC field isn’t included. The format of the 8-byte header is 4Dh, 41h, 43h, 01h, PKT_SIZE low and PKT_SIZE high A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 742 / 812...
  • Page 743 Length Out of Range Length Check Error CRC Error Receive Code Violation Carrier Event Previously Seen RXDV Event Previously Seen Packet Previously Ignored A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 743 / 812...

  • Page 744: Gmac

     Comprehensive status report for normal operation and transfers with errors  4KB TXFIFO for transmission packets and 16KB RXFIFO for reception packets  Programmable interrupt options for different operational conditions A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 744 / 812...

  • Page 745: Gmac Block Diagram

    6.12.2. GMAC Block Diagram TXFIFO RXFIFO TXFC RXFC G(MII) GMAC Interface Master MAC CSR DMA CSR RGMII Register AHB Slave A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 745 / 812...

  • Page 746: Transport Stream

     Configurable SPI transport stream generator for streams in DRAM memory  Support DMA for data transfer  Support interrupt  Support DVB-CSA V1.1 descrambler A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 746 / 812...

  • Page 747: Transport Stream Block Diagram

    TSC Port Parameter Register TSC_TSFMUXR TSC + 0x20 TSC TSF Input Multiplex Control Register TSC_OUTMUXR TSC + 0x28 TSC Port Output Multiplex Control Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 747 / 812...
  • Page 748 TSD + 0x04 TSD Status Register TSD_CWIR TSD + 0x1c TSD Control Word Index Register TSD_CWR TSD + 0x20 TSD Control Word Register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 748 / 812...

  • Page 749: Transport Stream Register Description

    0 – SPI 1 – SSI 15:2 TSInPort1Ctrl TS Input Port1 Control 0 – SPI 1 – SSI TSInPort0Ctrl TS Input Port0 Control A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 749 / 812...
  • Page 750 CLOCK signal polarity 0 : Rise edge capturing 1: Fall edge capturing ERROR signal polarity 0: High level active 1: Low level active A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 750 / 812...
  • Page 751 TSF1 Input Multiplex Control 0x0 –Data from TSG 0x1 –Data from TS IN Port0 0x2 –Data from TS IN Port1 Others – Reserved TSF0InputMuxCtrl A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 751 / 812...
  • Page 752 Read/Write Default Description 31:26 TSGSts Status for TS Generator 0: IDLE state 25:24 1: Running state 2: PAUSE state Others: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 752 / 812...
  • Page 753 TS Generator is running. 6.13.4.8. TSG PACKET PARAMETER REGISTER Register Name: TSG_PPR Offset: TSG+0x04 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 753 / 812...
  • Page 754 If set this bit, the interrupt would assert to CPU when all data in external DRAM are sent to TS PID filter. TSGFFIE TS Generator (TSG) Full Finish Interrupt Enable 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 754 / 812...
  • Page 755 Default Value: 0x0000_0000 Read/Write Default Description TSGCDF_N 31:16 TSG Clock Divide Factor (N) The Numerator part of TSG Clock Divisor Factor. 15:0 TSGCDF_D A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 755 / 812...
  • Page 756 It is in byte unit. The size should be 4-word (16 Bytes) align, and the lowest 4 bits should be zero. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 756 / 812...
  • Page 757 Default Description LostSyncThd 31:28 Lost Sync Packet Threshold It is used for packet sync lost by checking the value of sync A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 757 / 812...
  • Page 758 1: 192 bytes 2: 204 bytes 3: Reserved 6.13.4.16. TSF INTERRUPT ENABLE AND STATUS REGISTER Register Name: TSF_IESR Offset: TSF+0x08 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 758 / 812...
  • Page 759 TS PID Filter (TSF) Channel DMA status It is global status for 16 channel. It would clear to zero after all channels status bits are clear. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 759 / 812...
  • Page 760 Set by hardware, and can be cleared by software writing ‘1’. When both these bits and the corresponding DMA Interrupt Enable bits set, the TSF interrupt will generate. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 760 / 812...
  • Page 761 Channel Index m for Detecting PCR packet (m from 0 to 31) PCRLSB PCR Contest LSB 1 bit PCR[0] 6.13.4.22. TSF PCR DATA REGISTER Register Name: TSF_PCRDR Offset: TSF+0x24 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 761 / 812...
  • Page 762 PES Packet Enable for Channel 0~31 0: Disable 31:0 1: Enable These bits should not be changed during the corresponding channel enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 762 / 812...
  • Page 763 Address range of channel private registers is 0x40~0x7f. 6.13.4.27. TSF CHANNEL CONTROL REGISTER Register Name: TSF_CCTLR Offset: TSF+0x40 Default Value: 0x0000_0000 Read/Write Default Description 31:0 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 763 / 812...
  • Page 764 Default Value: 0x1fff_0000 Read/Write Default Description PIDMSK 31:16 0x1fff Filter PID Mask for Channel PIDVAL 15:0 Filter PID value for Channel A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 764 / 812...
  • Page 765 The maximum buffer size is 2MB. This size should be 4-word (16 Bytes) aligned. The LSB four bits should be zero. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 765 / 812...
  • Page 766 Register Name: TSD_CTLR Offset: TSD+0x00 Default Value: 0x0000_0000 Read/Write Default Description 31:2 DescArith Descramble Arithmetic 00: DVB CSA V1.1 Others: Reserved A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 766 / 812...
  • Page 767 6.13.4.38. TSD CONTROL WORD REGISTER Register Name: TSD_CWR Offset: TSD+0x20 Default Value: 0x0000_0000 Read/Write Default Description 31:0 Content of Control Word corresponding to the TSD_CWIR A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 767 / 812...

  • Page 768: Transport Stream Clock Requirement

    Requirement HCLK AHB bus clock Clock of TS Stream in SPI TS_CLK mode TSC_CLK TS serial clock from CCU TSC_CLK >=16*TS_CLK A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 768 / 812...

  • Page 769: Smart Card Reader

     Support configurable timing functions:Smart card activation time, Smart card reset time, Guard time, Timeout timers  Support synchronous and other non-ISO 7816 and non-EMV cards A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 769 / 812...

  • Page 770: Smart Card Reader Block Diagram

    Smart Card Reader Timing Diagram Please refer ISO/IEC 7816 and EMV2000 Specification. 6.14.4. Smart Card Reader Register List Module Name Base Address A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 770 / 812...

  • Page 771: Smart Card Reader Register Description

    This bit is set to ‘1’ when the scdetect input is active at least for a debounce time. SCDETPOL Smart Card Detect Polarity This bit set polarity of scdetect signal. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 771 / 812...
  • Page 772 When the deactivation is finished, the DEACT bit is automatically cleared. Activation. Setting of this bit initializes the activation sequence. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 772 / 812...
  • Page 773 SMART CARD READER INTERRUPT ENABLE REGISTER Register Name: SCR_INTEN Offset: 0x0004 Default Value: 0x00000000 Read/Write Default Description 31:24 SCDEA Smart Card Deactivation Interrupt Enable. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 773 / 812...
  • Page 774 RX FIFO Full Interrupt Enable. TXPERR TX Parity Error Interrupt Enable. TXDONE TX Done Interrupt Enable. TXFIFOTHD TX FIFO Threshold Interrupt Enable. TXFIFOEMPTY A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 774 / 812...
  • Page 775 ATR sequence fails. C2CFULL Two Consecutive Characters Limit Interrupt. When enabled, this interrupt is asserted if the time between two consecutive A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 775 / 812...
  • Page 776 TXREPEAT times or T=1 protocol is used. TXDONE TX Done Interrupt. When enabled, this interrupt is asserted after one character was transmitted to the smart card. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 776 / 812...
  • Page 777 Flush TX FIFO. TX FIFO is flushed, when ‘1’ is written to this bit. TXFIFOFULL TX FIFO Full. TXFIFOEMPTY TX FIFO Empty. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 777 / 812...
  • Page 778 The re-transmission of the character is requested using the error signal during the guard time. TXRPT A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 778 / 812...
  • Page 779 Register Name: SCR_LTIM Offset: 0x001c Default Value: 0x00000000 Read/Write Default Description 31:24 23:16 ATR Start Limit. This 16-bit register defines the maximum time A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 779 / 812...
  • Page 780 Smart Card Reader to the Smart Card. The value is in ETUs. The parity error is besides signaled during the guard time. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 780 / 812...
  • Page 781 4 bits. 6.14.5.11. SMART CARD READER FIFO DATA REGISTER Register Name: SCR_FIFO Offset: 0x0100 Default Value: 0x00000000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 781 / 812...
  • Page 782 S C C D I V s c c lk After the ATR is completed, the ETU can be changed according to Smart Card abilities. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 782 / 812...

  • Page 783: Scio Pad Configuration

    B A U D s c c lk Parameters F and D are defined in the ISO/IEC 7816-3 Specification. 6.14.7. SCIO Pad Configuration A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 783 / 812...

  • Page 784: Sata Host

    SATA_AHCI Timing Diagram Please refer to Serial ATA Specification Rev. 2.6 and Serial ATA Advanced Host Controller Interface (AHCI) Specification Rev. 1.1. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 784 / 812...

  • Page 785: Can

     64-byte receive buffers  Support one shot transmission option  Support two configurable filter modes  Support listen-only mode  Support self-test mode A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 785 / 812...

  • Page 786: Can System Block Diagram

    =TQ x (8 x TSEG1.3 + 4 x TSEG1.2 + 2 x TSEG1.1 + TSEG1.0 + 1) tseg1 =TQ x (4 x TSEG2.2 + 2 x TSEG2.1 + TSEG2.0 + 1) tseg2 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 786 / 812...

  • Page 787: Can Controller Register List

    CAN acceptance code 0 register CAN_ACPM 0x0044 CAN acceptance mask 0 register CAN_RBUF_RBACK 0x180~0x1b0 CAN transmit buffer for read back register A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 787 / 812...

  • Page 788: Can Controller Register Description

    0 - Normal operation. The error counters are stopped at the current value. Reset Mode 1 – Reset mode selected. Any message currently being A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 788 / 812...
  • Page 789 Set this bit to 1 to request to abort the current message transmission TRANS_REQ Transmission Request Set this bit to 1 to request to transmit a message A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 789 / 812...
  • Page 790 11001 - Acknowledge 11011 - Acknowledge delimiter 11010 - End of frame 10010 - Intermission 20:16 10001 - Active error flag A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 790 / 812...
  • Page 791 1 – controller is in the process of receiving a message 0 – nothing is currently being received TX_OVER Transmission Complete 1 – The last requested transmission has been successfully A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 791 / 812...
  • Page 792 This is a wirte-1-to-clear bit. ARB_LOST Arbitration Lost Interrupt Set when the controller loses arbitration and becomes a receiver This is a wirte-1-to-clear bit. ERR_PASSIVE A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 792 / 812...
  • Page 793 Receive Buffer. This is a wirte-1-to-clear bit. 6.16.5.5. CAN INTERRUPT ENABLE REGISTER Register Name: CAN_INTE_REG Offset: 0x10 Default Value: 0x0000_0000 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 793 / 812...
  • Page 794 1 – transmit interrupt enable 0 – transmit interrupt disable RX_EN Receive Interrupt Enable 1 – receive interrupt enable 0 - receive interrupt disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 794 / 812...
  • Page 795 These bits determine the time quanta (Tq) clock which is used to build up the individual bit timing. These bits are only writable in reset mode. [9:0] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 795 / 812...
  • Page 796 CAN RECEIVE MESSAGE REGISTER Register Name: CAN_RMSGC_REG Offset: 0x20 Default Value: 0x0000_0000 Read/Write Default Description 31:8 RX_MSG_CNT CAN receive message counter A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 796 / 812...
  • Page 797 6.16.5.12. CAN TX/RX MESSAGE BUFFER 1 REGISTER (TRANSFER MODE) Register Name: CAN_TXBUF1 Offset: 0x44 Default Value: 0x0000_0000 Read/Write Default Description 31:8 ID[28:21] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 797 / 812...
  • Page 798 Register Name: CAN_TXBUF4 Offset: 0x50 Default Value: 0x0000_0000 Read/Write Default Description 31:8 SDATA2_EID SFF-TX data byte2[7:3] / EFF-ID[4:0] SDATA2 SFF-TX data byte2[2:0] A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 798 / 812...
  • Page 799 Register Name: CAN_TXBUF8 Offset: 0x60 Default Value: 0x0000_0000 Read/Write Default Description 31:8 SDATA6_EDATA4 SFF-TX data byte 6 / EFF- TX data byte 4 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 799 / 812...
  • Page 800 6.16.5.23. CAN TX/RX MESSAGE BUFFER 12 REGISTER (TRANSFER MODE) Register Name: CAN_TXBUF12 Offset: 0x70 Default Value: 0x0000_0000 Read/Write Default Description 31:8 EDATA8 EFF- TX data byte 8 A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 800 / 812...
  • Page 801 Each register is 32-bit width register, but only the lower 8 bits are valid to access. All higher 24 bits will return 0 when be read. A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 801 / 812...

  • Page 802: Keypad

     Support industry-standard AMBA Peripheral Bus (APB) and is fully compliant with the AMBA Specification, Revision 2.0.  Interrupt for key press or key release  Internal debouncing filter to prevent the switching noises A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 802 / 812...

  • Page 803: Keypad Interface Register List

    When set to ‘1’, the corresponding input is masked. Keypad Column Output Mask 15:8 When set to ‘1’, the corresponding output is masked. IF_ENB Keypad Interface enable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 803 / 812...
  • Page 804 Register Name: KP_INT_CFG Offset: 0x08 Default Value: 0x0000_0000 Read/Write Default Description 31:2 REDGE_INT_EN Keypad input rising edge (key release) interrupt enable 0: Disable A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 804 / 812...
  • Page 805 Default Value: 0xffff_ffff Read/Write Default Description [8i+7:8i COL_STA0 0xff Keypad row input byte for column n scan (n from 0 to 3) (i=0~3) A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 805 / 812...

  • Page 806: Keypad Interface Special Requirement

    Keypad row input byte for column n scan (n from 4 to 7) 6.17.4. Keypad Interface Special Requirement 6.17.4.1. KEYPAD INTERFACE PIN LIST Port Name Width Direction Description KP_OUT KP_IN A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 806 / 812...

  • Page 807: Appendix A

    Appendix A Glossary A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 807 / 812...
  • Page 808 The hardware block that interfaces with different image CMOS Sensor Interface sensor interfaces and provides a standard output that can be used for subsequent image processing A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 808 / 812...
  • Page 809 An architecture consisting of an embedded storage solution eMMC Embedded Multi-Media Card with MMC interface, flash memory and controller, all in a small BGA package A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 809 / 812...
  • Page 810 Low Resolution Analog to A module which can transfer analog signals to digital LRADC Digital Converter signals A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 810 / 812...
  • Page 811 Phase Alternating Line broadcast television systems in many countries A method used to digitally represent sampled analog Pulse Code Modulation signals A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 811 / 812...
  • Page 812 Universal Serial Bus USB DRD functions and is fully compliant with the On-The-Go Dual-Role Device Supplement to the USB 2.0 Specification, Revision 1.0a A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 812 / 812...

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