Table of Contents
Advertisement
Quick Links
Download this manual
See also:
User Manual
Intel® PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Product Features
High Performance Processor
■
— Intel® XScale™ Microarchitecture
— 32 KB Instruction Cache
— 32 KB Data Cache
— 2 KB "mini" Data Cache
— Extensive Data Buffering
Intel® Media Processing Technology
■
— Enhanced 16-bit Multiply
— 40-bit Accumulator
Flexible Clocking
■
— CPU clock from 100 to 400 MHz
— Flexible memory clock ratios
— Frequency change modes
Rich Serial Peripheral Set
■
— AC97 Audio Port
2
— I
S Audio Port
— USB Client Controller
— High Speed UART
— Second UART with flow control
— UART with hardware flow control
— FIR and SIR infrared comm ports
February, 2004
Low Power
■
— Less than 500 mW Typical Internal
Dissipation
— Supply Voltage may be Reduced to
1.00 V
— Low Power/Sleep Modes
High Performance Memory Controller
■
— Four Banks of SDRAM - up to 100 MHz
— Five Static Chip Selects
— Support for PCMCIA or Compact Flash
— Companion Chip interface
Additional Peripherals for system
■
connectivity
— Multimedia Card Controller (MMC)
— SSP Controller
— Network SSP controller for baseband
— I2C Controller
— Two Pulse Width Modulators (PWMs)
— All peripheral pins double as GPIOs
Hardware debug features
■
Hardware Performance Monitoring features
■
Order Number: 278805-002
Data Sheet
Advertisement
Table of Contents
Related Manuals for Intel PXA255
Summary of Contents for Intel PXA255
-
Page 1: Data Sheet
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Data Sheet Product Features High Performance Processor Low Power ■ ■ — Intel® XScale™ Microarchitecture — Less than 500 mW Typical Internal Dissipation — 32 KB Instruction Cache — Supply Voltage may be Reduced to —... - Page 2 The PXA255 processor EMTS Data Sheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
-
Page 3: Table Of Contents
PXA255 Processor — Electrical, Mechanical, and Thermal Specification Contents About This Document .................... 7 Functional Overview ....................7 Package Information ....................8 Package Introduction..................8 3.1.1 Functional Signal Definitions ............8 3.1.1.1 PXA255 Processor Signal Pin Descriptions .....8 Package Power Ratings ................22 Electrical Specifications ..................22 Absolute Maximum Ratings................. - Page 4 Processor Pin Types ..................... 9 Pin and Signal Descriptions for the PXA255 Processor........9 Pin Description Notes..................18 PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order ..20 θ and Maximum Power Ratings................ 22 Absolute Maximum Ratings ................23 Power Consumption Specifications for PXA255 processor ........
-
Page 5: Revision History
PXA255 Processor — Electrical, Mechanical, and Thermal Specification Revision History Date Revision Description March 2003 -001 First public release of the EMTS February 2004 -002 Updated 400 MHz Idle mode power. Data Sheet... - Page 6 PXA255 Processor — Electrical, Mechanical, and Thermal Specification Data Sheet...
-
Page 7: About This Document
A rich set of serial devices as well as general-system resources provide enough compute and connectivity capability for many applications. For details on the programming model and theory of operation of each of these units, refer to the Intel® PXA255 Processor Developer's Manual. For the processor block diagram, refer to Figure 1, “Processor Block Diagram”... -
Page 8: Package Information
3.1.1 Functional Signal Definitions 3.1.1.1 PXA255 Processor Signal Pin Descriptions Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 describes the signal definitions for the PXA255 processor. Figure 2, “PXA255 processor” on page 19 illustrates the physical characteristics of the PXA255 processor. -
Page 9: Processor Pin Types
CMOS bidirectional, Hi-Z Analog Input Analog output IAOA Analog bidirectional Supply pin (either VCC or VSS) Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9) Pin Name Type Signal Descriptions Reset State Sleep State Memory Controller Pins Memory address bus. - Page 10 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9) Pin Name Type Signal Descriptions Reset State Sleep State SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of SDCKE[1] SDRAM.
- Page 11 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9) Pin Name Type Signal Descriptions Reset State Sleep State LCD display data. (output) Transfers pixel information L_DD[15]/ from the LCD controller to the external LCD panel.
- Page 12 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 4 of 9) Pin Name Type Signal Descriptions Reset State Sleep State LCD display data. (output) Transfers pixel information L_DD[9]/ from the LCD controller to the external LCD panel.
- Page 13 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 5 of 9) Pin Name Type Signal Descriptions Reset State Sleep State FFRI/ Pulled High - ICOCZ Full function UART ring indicator. (input) Note [3] Note[1] GPIO[38]...
- Page 14 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 6 of 9) Pin Name Type Signal Descriptions Reset State Sleep State LCD display data. (output) Transfers pixel information L_DD[10]/ from the LCD controller to the external LCD panel.
- Page 15 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9) Pin Name Type Signal Descriptions Reset State Sleep State AC97 Controller and I S Controller Pins AC97 audio port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA255 processor processor and Codec 1.
- Page 16 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9) Pin Name Type Signal Descriptions Reset State Sleep State TEXTAL 32 kHz crystal output. No external caps are required. Note [2] Note [2] LCD display data. (output) Transfers pixel information...
- Page 17 Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9) Pin Name Type Signal Descriptions Reset State Sleep State Reset out. (output) Asserted when nRESET is asserted Driven low during and deasserts after nRESET is de-asserted but before...
-
Page 18: Pin Description Notes
Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 in the Intel® PXA255 Processor Developers Manual. If selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the sleep-state register is driven out onto the pin and held there while the PXA255 processor is in sleep mode. -
Page 19: Pxa255 Processor
Package Information Figure 2. PXA255 processor Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 20: Pxa255 Processor 256-Lead 17X17Mm Mbga Pinout - Ballpad No. Order
Package Information Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 1 of 3) Ball # Signal Ball # Signal Ball # Signal VCCN VCCQ nSDCAS L_DD[13]/GPIO[71] VSSQ VCCN L_DD[12]/GPIO[70] USB_P SDCLK[1] L_DD[11]/GPIO[69] VCCQ VSSQ L_DD[9]/GPIO[67]... - Page 21 Package Information Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 2 of 3) Ball # Signal Ball # Signal Ball # Signal L_DD[8]/GPIO[66] VCCQ VSSQ VCCQ NSSPTXD/GPIO[83] L_DD[2]/GPIO[60] NSSPSFRM/GPIO[82] VSSQ nSDCS[0] BITCLK/GPIO[28] nSDCS[3] nTRST MD[24]...
-
Page 22: Package Power Ratings
Electrical Specifications Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 3 of 3) Ball # Signal Ball # Signal Ball # Signal nBATT_FAULT VCCN MD[3] nVDD_FAULT MD[13] MD[5] GPIO[3] VCCN nCS[1]/GPIO[15] PXTAL DREQ[0]/GPIO[20] nCS[3]/GPIO[79] PEXTAL... -
Page 23: Power Consumption Specifications
These figures are important when considering battery size and optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load. The typical power consumption for the PXA255 processor is calculated using these conditions: •... -
Page 24: Power Consumption Specifications For Pxa255 Processor
All voltages at nominal values • Nominal case temperature Table 8 contains power consumption numbers for the PXA255 processor. Table 8. Power Consumption Specifications for PXA255 processor (Sheet 1 of 2) Symbol Description Typical Maximum Units 400 MHz active mode, Maximum: V =1.65V, V... -
Page 25: Operating Conditions
Electrical Specifications Table 8. Power Consumption Specifications for PXA255 processor (Sheet 2 of 2) Symbol Description Typical Maximum Units Current and V Current Total Power TOTAL Sleep mode, Maximum: V =0V, V =3.3V, Temp=Room and V Current µA Fast sleep wakeup mode, Maximum: V =1.0/1.1/1.3V, V... -
Page 26: Targeted Dc Specifications
I/O pins (VO=VOH) Output Low Current, all standard, high- IOL_H strength output and I/O pins (VO=VOH) Output Low Current, all standard, low- IOL_L strength output and I/O pins (VO=VOH) Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 27: Targeted Ac Specifications
Input, Output, and I/O Pin AC Operating Conditions” shows the AC operating conditions for the high- and low-strength input, output, and I/O pins. All AC specification values are valid for the entire temperature range of the device. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 28: Oscillator Electrical Specifications
Input Leakage, TXTAL µA CIN_XT Input Capacitance, TXTAL/TEXTAL tS_XT Stabilization Time Board Specifications RP_XT Parasitic Resistance, TXTAL/TEXTAL to any node MΩ CP_XT Parasitic Capacitance, TXTAL/TEXTAL, total COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 29: 3.6864 Mhz Oscillator Specifications
Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system; therefore, it is not recommended. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 30: Reset And Power Ac Timing Specifications
On the processor, it is important that the VCCQ power supply be powered up before or at the same time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up anytime within the specification shown in Figure 3 Table Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 31: Power-On Reset Timing
Delay between VCC, PLL_VCC stable tD_NRESET — — and nRESET de-asserted Delay between nRESET de-asserted tD_OUT 18.1 — 18.2 and nRESET_OUT de--asserted Delay between nRESET_OUT tD_NCS0 — deasserted and nCS0 asserted Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 32: Hardware Reset Timing
Note: nBA TT_FAULT and nVDD_F AULT must be high before nRESET is deasserted Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is or the Cotulla will enter Sleep Mode de-asserted or the PXA255 processor enters sleep mode. Table 16. Hardware Reset Timing Specifications Symbol... -
Page 33: Sleep Mode Timing
Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Figure 6, “Sleep Mode Timing” on page 34 and detailed in Figure 18, “Sleep Mode Timing Specifications” on page 34 is the required timing parameters for sleep mode. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 34: Sleep Mode Timing
D_F A UL T nRESET_OUT DSM_OUT Note: nBA TT_FAULT must be high or Cotulla will not exit Sleep Mode Note: nBATT_FAULT must be high or the PXA255 processor will not exit sleep mode. Table 18. Sleep Mode Timing Specifications Symbol... -
Page 35: Memory Bus And Pcmcia Ac Specifications
MD(31:0), DQM(3:0) hold after nPWE de-asserted tvlioDHR MD(31:0) read data hold after nOE de-asserted tvlioRDYH RDY hold after nOE, nPWE de-asserted tvlioNPWE nPWE, nOE high time between beats of write or read data Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 36: Card Interface (Pcmcia Or Compact Flash) Ac Specifications
3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 37: Peripheral Module Ac Specifications
Figure 8, “SSP AC Timing Definitions” on page 38 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SCLK_C. Values for the parameters are given in Table 24, “SSP AC Timing Specifications” on page Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 38: Boundary Scan Test Signal Timings
TBSOV1 TDO valid delay Relative to falling edge of TCK TOF1 TDO float delay Relative to falling edge of TCK TOV12 All outputs (non-test) valid delay Relative to falling edge of TCK Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification... -
Page 39: Ac Test Conditions
AC Test Conditions The AC specifications in Section 4.5, “Targeted AC Specifications” on page 27 are tested with a 50 pF load indicated in Figure Figure 9. AC Test Load Output Ball = 50pF Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification...
Need help?
Do you have a question about the PXA255 and is the answer not in the manual?
Questions and answers