Nabu 1100 System Technical Manual page 23

zeD
Micro-
proceuor
Family
zeD CPU
aegilte...
The Zilog
zao
microprocessor is the central
element of a comprehensive microprocessor
product famHy. This family works together in
most applications with minimum requirements
for additional logic, facilit(lting the design of
efficient and cost-effective microcomputer-
baaed systems.
Zilog has designed five components to pro-
vide extensive support for the 280 micro-
processor. These are:
• The PIO (Parallel Input/Output) operates in
both data-byte I/O transfer mode (with
handshaking) and in bit mode (without
handshaking). The PIO may be conflg-
ured to interface with standard parallel
peripheral devices such as printers,
tape punches, and keyboards.
• The eTC (Counter/Timer Circuit) features
four programmable 8-bit counter/timers,
Figure 4 shows three groups of registers
within the
zao
CPU. The flrst group consists of
duplicate sets of 8-bit registers: a principal set
and an alternate set (designated by , [prime],
e.g., A'). Both sets consist of the Accumula-
tor Register, the Flag Register, and six
general-purpose registers. Transfer of data
between these duplicate sets of registers is
accomplished by use of "Exchange" instruc-
tions. The result is faster response to interrupts
and easy, efficient implementation of such ver-
satile programming techniques as background-
each of which has an 8-bit prescaler. Each
of the four channels may be configured to
operate in either counter or timer mode.
• The DMA (Direct Memory Access) con-
troller provides dual port data transfer
operations and the ability to terminate data
transfer as a result of a pattern match.
• The SIO (Serial Input/Output) controller
offers two channels. It is capable of
operating in a variety of programmable
modes for both synchronous and asyn-
chronous communication, including
Bi-Synch and SDLC.
• The DART (Dual Asynchronous Receiver/
Tr(lnsmitler) device provides low cost
asynchronous serial communication. It has
two channels and a full modem control
interface.
foreground data processing. The second set of
registers consists of six registers with assigned
functions. These are the I (Interrupt Register),
the R (Refresh Register), the IX and IY (Index
Registers), the SP (Stack Pointer), and the PC
(Program Counter). The third group consists of
two interrupt status flip-flops, plus an addi-
tional pair of flip-flops which assists in identi-
fying the interrupt mode at any particular
time. Table I provides further information on
these registers,
A
-'CCUMULATOM
F
FLAG
REGISTE~ A'
A-CCUMUlATOR
F'
HAG REGISTER
•
QI&:NERAL P-U"P08E C
GENEFIAl
PU~POSE
.'
GENERAL. PuFlPOSE C'
GENERAL PURPOSE
D Q,ENt:F1Al PURPose E
Gf:.NEMAL PURPOSE
D' IlEN£RAl puRPOSE E'
GENERAL PURPOSE
H GE:NERA'I. PURPOSE L G£H£AAL P-uRPOSE H'
OEN£RAl puRPOSE
L'
GENERAL PURPO!!
_ - - - - - - - ' . BITS - - - - - - -_ _
IX jNOEX REGISTER
IY fNDEX REGISTER
SP STACK POINrER
PC
P~OGAAM
COUNTEFl
I INtERtlUfIT VECTOR
I
fl. MEMORV REfRESH
..
is
BITS
--
INTERftUfllT FLIP·FLOPS
sUfu$
c:J GI----.
~
INTEMUPTS D'SABlED STOAl' IF.,
4
~
:
tNTEiRFlUPT$ ENAeLED DURINQ
Alii
SERVICE
INTERRUPT MODE HIP·FlOPS
c:E
IHTEAIUJPT MODE 0
HOT USED
lNTERftl,lPT UQDf: ,
INTEfUlUpl MODE .2
2001-0213
Figure 4.. CPU Registe"
7