Rebi Mode (Reduced Eight Bit Interface); Rebi - Individual Channel Byte Ordering - Channel 0 Example; Rebi - Lane To Functional Pin Mapping - Texas Instruments TLK3134 Data Manual

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2.7.7 REBI Mode (Reduced Eight Bit Interface)

DATA CHANNEL TRANSMIT DATA 4 BITS
NUMBER
Channel 0
Channel 1
Channel 2
Channel 3
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXD_[3:0] Data0[3:0]
RXCLK_[0]
RXD_[3:0]
Data0[3:0]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXD_[3:0] Data0[3:0]
RXCLK_[0]
RXD_[3:0] Data0[3:0]
Figure 2-13. REBI – Individual Channel Byte Ordering – Channel 0 Example
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-10. REBI – Lane To Functional Pin Mapping
RECEIVE DATA 4 BITS
(INPUT)
TXD_[3:0]
TXD_[11:8] RXD_[11:8]
TXD_[19:16] RXD_[19:16]
TXD_[27:24] RXD_[27:24]
Data0[7:4]
Data0[7:4]
Data0[7:4]
Data0[7:4]
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Product Folder Link(s):
TRANSMIT CLOCK
(OUTPUT) (INPUT)
RXD_[3:0] TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
DDR Source Centered Timing
TXCLK_[0]
TXD_[3:0]
RXCLK_[0]
RXD_[3:0]
TXCLK_[0]
TXD_[3:0]
RXCLK_[0]
RXD_[3:0]
TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
RXCLK_[2]
RXCLK_[3]
(Nibble Order = 0)
Data0[7:4] Data0[3:0]
Data0[7:4] Data0[3:0]
DDR Source Aligned Timing
(Nibble Order = 0)
Data0[7:4] Data0[3:0]
Data0[7:4] Data0[3:0]
Detailed Description
TLK3134
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