The 1/0 Backplane - HP Integral Personal Computer Service Manual

.. 10
'unell_.
De8Ol'lption
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NPSO and NPSI are the port select signals for ports A and B, respectively. The NPSO or NPSI signal
indicates to a card that it is being accessed within its 'port selected' address space. The signal, when
low, indicates that BAI through BA23, BR/NW, NBUD, and NBLO are valid for the selected port.
NBAS is the address strobe signal. This signal, when low, indicates that BAI through BA23 and
BR/NW are valid. The address strobe signal is used by
memory
modules since they must be accessed
outside the
'port
selected' address space for the I/O port.
NBIMA is the 'I'm addressed' signal. A memory module uses this signal to indicate (by a low signal)
that it has been previously allocated the address specified by the current bus cycle.
NBDTACK is the data transfer acknowledge signal. This signal (by going low) indicates that the data
transfer portion of a bus cycle is completed. When the mainframe recognizes NBDTACK during a read
cycle, data is latched and the bus cycle is terminated. When NBDTACK is recognized during a write
cycle, data'
is
removed from the bus and the cycle
is
terminated.
NBRESET is the reset signal. This signal goes low for at least 100 ms when the
power
is turned on. It
also goes low for at least 100 ms starting a minimum of 1 ms before the power goes off. The
NBRESET signal goes low for 15.5
IJ.S
in response to the RESET instruction.
NBIRO, NBIR1, NBIR2, and NBIR3 are the interrupt request signals. Interfaces assert these lines low to
request asynchronous interrupts at different interrupt levels. External interrupt request levels NBIRO
through NBIR3 correspond to internal interrupt request levels IR3 through IR6
1
respectively.
NBDMARQ is the direct memory access request signal. The Integral PC does not support direct mem-
ory access. The NBDMARQ pins on the port A and port B connectors are wired together to facilitate
bus expander testing.
GRIN and GROUT
are
not used by the Integral PC. In the I/O port connectors the GRIN pins are tied
low, and the GROUT pins are left open.
1.8.3 The 1/0 Backplane
The I/O backplane assembly provides the link between external I/O devices and the external I/O bus.
It consists of the I/O backplane peA and a guide
asse~bly
to hold interfaces and memory modules.
The I/O backplane peA has two connectors, one for port A and one for port B.
The I/O backplane assembly can support a total power requirement of 9 watts for both ports. An
individual port can support a 6-watt
power
requirement. Thus, up to one 6-watt interface and one 3-
watt interface (or memory module) may be installed.
Notel You can expand the I/O capability of the Integral PC to 10 ports by using two bus
expanders as shown in figure 5-2. Each bus expander has its own power supply.
Each I/O port supports the Level 0 Subset of the P-bus (the Personal Computer Group compatible
bus) with the exception that the I/O backplane connectors provide the outer two rows of pins only
(row A and rowe). Refer to table 10-4 for the connector pin assignments.