Altera Stratix II GX User Manual page 158

Native Modes
2–146
Stratix II GX Device Handbook, Volume 2
Basic Single-Width Mode
Use the Basic single-width mode for custom protocols that are not part of
the pre-defined supported protocols, for example PIPE. With some
restrictions, the following PCS blocks are available:
■
Transmitter phase compensation FIFO buffer
■
Transmitter byte serializer
■
8B/10B encoder
■
Word aligner
■
Rate matcher
■
8B/10B decoder
■
Byte deserializer
■
Byte ordering block
■
Receiver phase compensation FIFO buffer
The byte ordering block is available only in reverse serial loopback
configuration in Basic mode. The rate matcher is coupled with the 8B/10B
code groups, which requires the use of the 8B/10B encoder or decoder
either in the PCS or PLD logic array.
Basic Single-Width Mode with x4 Clocking
In basic single-width mode, the ALT2GXB MegaWizard provides a ×4
option under the Which subprotocol will you be using? option. If you
select this option, all four transmitter channels within the transceiver
block are clocked by clocks generated from the central clock divider block
(refer to "Transmitter Clocking (Bonded Channels)" on page
low-speed clock from the central clock divider block clocks the bonded
transmitter PCS logic in all four channels. This reduces the transmitter
channel-to-channel skew within the transceiver block. Each receiver
channel within the transceiver block is clocked individually by the
recovered clock from its own clock recovery unit (CRU).
1
Configuring transceivers in this mode yields low transmitter
channel-to-channel skew within a transceiver block. It does not
provide skew reduction for channels placed across transceiver
blocks.
2–29). The
Altera Corporation
October 2007