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P H 4 4 0 N L X M o t h e r b o a r d U s e r G u i d e
Code
36h
37h
38h
39h
3Ah
3Ch
3Dh
42h
44h
45h
46h
48h
49h
4Ah
4Bh
4Ch
4Eh
50h
51h
52h
54h
56h
58h
59h
5Ah
5Bh
5Ch
5Eh
60h
62h
64h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Eh
MITSUBISHI ELECTRIC MOTHERBOARD DIVISION
POST Routine Description
Warm start shut down
Reinitialise the chipset (MB only)
Shadow system BIOS ROM
Reinitialise the cache (MB only)
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialise interrupt vectors
Initialise BIOS interrupts
POST device initialisation
Check ROM copyright notice
Check video configuration against CMOS
Initialise PCI bus and devices
Initialise all video adapters in system
Display QuietBoot screen
Shadow video BIOS ROM
Display BIOS copyright notice
Display CPU type and speed
Initialise EISA board
Test keyboard
Set key click if enabled
Enable keyboard
Test for unexpected interrupts
Initialise POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Test RAM between 512 and 640 KB
Base address
Test extended memory
Test extended memory address lines
Jump to UserPatch1
Configure advanced cache registers
Initialise Multi Processor APIC
Enable external and CPU caches
Setup System Management Mode (SMM) area
Display external L2 cache size
Customise defaults
Display shadow- area message
Display possible high address for UMB recovery
S e p t e m b e r 1 9 9 8
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