Table of Contents
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Index
Numerics
32-bit
109
addressing
9
applications
24
data format
36
instructions
operands, in 64-bit mode
6, 67
operations
single-precision FP format
virtual-to-physical-address
translation
32-bit mode
31
address space
address translation
63
addresses
153
FPU operations
TLB entry format
4th Floor
B-dorm. See Alco Hall
64-bit
109
addressing
9
ALU
bus, address and data
24
data format
double-precision FP format
floating-point registers
9
FPU
internal data path widths
6, 39, 67
operations
11
System interface
virtual-to-physical-address
translation
MIPS R4000 Microprocessor User's Manual
39
164
65
65, 95
81
201
164
156
381
66
64-bit mode
32-bit operands, handling of
31
address space
address translation
63
addresses
153
FPU operations
TLB entry format
A
58
address acceleration
Address Error exception
58
address prediction
address space identifier (ASID)
address spaces
32-bit translation of
64-bit translation of
address space identifier (ASID)
64
physical
63
virtual
virtual-to-physical translation of
addressing
24
and data formats
24
big-endian
73
Kernel mode
24
little-endian
26
misaligned data
69
Supervisor mode
67
User mode
virtual address translation
See also address spaces
Alco Hall vs. Acid. See game, softball
application software, compatibility with
MIPS R2000, R3000, and R6000
6
processors
architecture
9
64-bit
11
superpipeline
array, page table entry (PTE)
ASID. See address space identifier
39
66, 95
81
127
64
65
66
64
64
95
102
I-1
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