Page 1: Hard Disk Drive Specifications
IBM storage products - official published specifications Hard disk drive specifications Travelstar 48GH, 30GN & 15GN 2.5 inch ATA/IDE hard disk drive Models: IC25T048ATDA05 IC25N010ATDA04 IC25N030ATDA04 IC25N007ATDA04 IC25N020ATDA04 IC25N006ATDA04 IC25N015ATDA04 IC25N005ATDA04 IC25N012ATDA04 Revision 2.0 10 January 2002 S07N-7909-09 Publication #1530...
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Page 3 Hard disk drive specifications Travelstar 48GH, 30GN & 15GN 2.5 inch ATA/IDE hard disk drive Models: IC25T048ATDA05 IC25N010ATDA04 IC25N030ATDA04 IC25N007ATDA04 IC25N020ATDA04 IC25N006ATDA04 IC25N015ATDA04 IC25N005ATDA04 IC25N012ATDA04 Revision 2.0 10 January 2002 S07N-7909-09 Publication #1530...
Page 4 IBM may have patents or pending patent applications covering subject matter in this document. The furnishing of this document does not give you any license to these patents. You can send license inquiries, in writing, to the IBM Director of Commercial Relations, IBM Corporation, Armonk, NY 10577.
Page 5: Table Of Contents
Table of contents ..............Figures .
Page 6 ........... . . 6.4.6 Load/unload .
Page 7 ..........9.0 Deviations from standard .
Page 8 ........11.10 Address Offset Feature (vendor specific) .
Page 9 ........13.33.2 Device Attributes Data Structure ......13.33.3 Device Attribute Thresholds data structure .
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Page 11: Figures
Figures ..........Figure 1.
Page 12 ..... . Figure 46. Ultra DMA cycle timings (Device Terminating Read) ......Figure 47.
Page 13 ........Figure 92. Read Buffer command (E4h) .
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Page 15: Introduction
1.0 Introduction This document describes the specifications of the IBM Travelstar 2.5-inch, ATA/IDE interface hard disk drive with the following model numbers: ! IC25T048ATDA05 (48 GB) ! IC25N030ATDA04 (30 GB) ! IC25N020ATDA04 (20 GB) ! IC25N015ATDA04 (15 GB) ! IC25N012ATDA04 (12 GB) ! IC25N010ATDA04 (10 GB) ! IC25N007ATDA04 (7.5 GB)
Page 16 Gb/sq.in. 1 000 000 000 bits per square inch (32 ft/sec) per Hertz ground hexadecimal head disk assembly hard disk drive hertz Input integrated lead suspension imped impedance Input/Output International Standards Organization 1,000 bytes Mbits/sec 1,000,000 bits per second Kbpi 1,000 Bit Per Inch kgf-cm kilogram (force)-centimeter...
Page 17: References
Trk. track transistor-transistor logic Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.2 References ! ATA/ATAPI-5 (T13/1321D Revision 3) 1.3 General caution ! Do not apply force to the top cover (See the figure title "Handling Precaution 1" on page 4). ! Do not cover the breathing hole on the top cover (See the figure title "Handling Precaution 2"...
Page 18: Drive Handling Precautions
1.4 Drive handling precautions Do not press on the drive cover during handling. Figure . Handling Precaution 1 Figure . Handling Precaution 2 Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 19: General Features
2.0 General features ! Height MCC Compliance - 2.5 inch form factor - height of 12.5 ± 0.2 mm (48 GB model) and 9.5 ± 0.2 mm (all other models) ! Capacities of 48 GB, 30 GB, 20 GB, 15 GB, 12 GB, 10 GB, 7.5 GB, 6 GB, and 5 GB ! 512 bytes/sector ! Ultra ATA/100 (Enhanced IDE) conforming to ATA-5 ! Integrated controller...
Page 20 Note: Mounting screw position is # Incompatible with DBOA, DMCA, DCRA, DSOA, and DPRA models # Compatible with DTNA, DLGA, DDLA, DTCA, DPLA, DYKA, DYLA, DADA, DKLA, DBCA, DCXA, DCYA, DARA, and DJSA models Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 21: Part 1. Functional Specification
Part 1. Functional specification Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
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Page 23: Fixed Disk Subsystem Description
3.0 Fixed disk subsystem description 3.1 Control Electronics The control electronics works with the following functions: ! AT Interface Protocol ! Embedded Sector Servo ! No-ID formatting ! Multizone recording ! Code: 96/104 MTR ! ECC on-the-fly ! Enhanced Adaptive Battery Life Extender 3.2 Head disk assembly data The following technologies are used in each model: ! Pico Slider...
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Page 25: Fixed Disk Characteristics
4.0 Fixed disk characteristics 4.1 Default logical drive parameters The following table lists the default logical drive parameters by drive model number. Model Capacity Word 1 Word 3 Word 6 Word Customer (GB) (Cyl) (Head) (Sect/Trk) 60–61 Usable (LBA) Data Bytes IC25T048ATDA05-0 16,383 596A690h...
Page 26: Data Sheet
Description 12 GB model 10 GB model 7.5 GB model 6 GB model 5 GB model Physical Layout Bytes per Sector Sectors per Track 280–540 280–540 336–640 280–540 280–540 Number of Heads Number of Disks Logical Layout Number of Heads Number of Sectors/ Track Number of Cylinders...
Page 27: Cylinder Allocation
4.4 Cylinder Allocation 48-GB model Zone Cylinder Number of Sectors per Track 0-2047 2048-4095 4096-6143 6144-7679 7680-9215 9216-11519 11520-13567 13568-15615 15616-17663 17664-19711 19712-21759 21760-23551 23552-25599 25600-27647 27648-28159 28160-28671 Figure 6. Cylinder allocation - 48-GB model (IC25T048ATDA05) 30-GB model Zone Cylinder Number of Sectors per Track 0-767 768-2815...
Page 28: Figure 8. Cylinder Allocation - 20-Gb Model (Ic25N020Atda04)
20-GB model Zone Cylinder Number of Sectors per Track 0-2047 2048-3071 3072-4351 4352-6655 6656-8959 8960-11263 11264-13567 13568-15615 15616-17151 17152-18175 18176-20479 20480-22527 22528-24575 24576-26623 26624-27647 27648-28671 Figure 8. Cylinder allocation - 20-GB model (IC25N020ATDA04) 15-GB, 7.5-GB models Zone Cylinder Number of Sectors per Track 0-767 768-2815 2816-5119...
Page 29: Figure 10. Cylinder Allocation - 12-Gb, 10-Gb, 6-Gb, 5-Gb Models
12-GB, 10-GB, 6-GB, 5-GB models Zone Cylinder Number of Sectors per Track 0-2047 2048-4095 4096-5887 5888-7679 7680-9471 9472-11519 11520-13311 13312-15615 15616-17663 17664-19967 19968-22271 22272-24063 24064-25599 25600-27135 27136-28159 28160-28671 Figure 10. Cylinder allocation - 12-GB, 10-GB, 6-GB, 5-GB models (IC25N012ATDA04, IC25N010ATDA04, IC25N006ATDA04, IC25N005ATDA04,) Travelstar 48GH, 30GN &...
Page 30: Performance Characteristics
4.5 Performance characteristics File performance is characterized by the following parameters: ! Command Overhead ! Mechanical Positioning ! Seek Time ! Latency ! Data Transfer Speed ! Buffering Operation (Look ahead/Write Cache) Note: All the above parameters contribute to file performance. There are other parameters which contri- bute to the performance of the actual system.
Page 31: Mechanical Positioning
4.5.2 Mechanical positioning 4.5.2.1 Average seek time (including settling) Command Type Typical (ms) Max (ms) Read Write Figure 12. Mechanical positioning performance Typical and Max are defined throughout the performance specification as follows: Typical Average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions.
Page 32: Figure 14. Single Track Seek Time
4.5.2.3 Single track seek time (without command overhead, including settling) Command Type Typical (ms) Maximum (ms) Read Write Figure 14. Single track seek time Single track seek is measured as the average of one (1) single track seek from every track in both directions (inward and outward).
Page 33: Operating Modes
4.5.3 Operating modes Operating mode Description Spin-Up Start up time period from spindle stop or power down. Seek Seek operation mode Write Write operation mode Read Read operation mode Performance The device is capable of responding immediately to idle media access requests All electronic components remain powered and the full frequency servo remains operational.
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Page 35: Data Integrity
5.0 Data integrity 5.1 Data loss on power off ! Data loss will not be caused by a power off during any operation but the write operation. ! A power off during a write operation causes the loss of any received or resident data that has not been written onto the disk media.
Page 36: Write Safety
5.4 WRITE safety The drive ensures that the data is written into the disk media properly. The following conditions are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked. ! Head off track ! External shock ! Low supply voltage...
Page 37: Ecc
5.8 ECC The 40-byte three interleaved ECC processor provides user data verification and correction capability. The first 4 bytes of ECC are check bytes for user data and the other 36 bytes are Read Solomon ECC. Each interleave has 12 bytes for ECC. Hardware logic corrects up to 15 bytes (5 bytes for each interleave) errors on-the-fly.
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Page 39: Specification
6.0 Specification 6.1 Environment 6.1.1 Temperature and humidity Operating conditions Temperature 5 to 55°C (See Note) Relative humidity 8 to 90% noncondensing Maximum wet bulb temperature 29.4°C noncondensing Maximum temperature gradient 20°C/hour Altitude –300 to 3048 m (10,000 ft) Non operating conditions Temperature –40 to 65°C Relative humidity...
Page 40: Magnetic Fields
6.1.1.1 Corrosion test The hard disk drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50°C/90%RH (relative humidity) for one week followed by a temperature humidity drop to 25°C/40%RH in 2 hours. 6.1.2 Magnetic fields The disk drive will withstand radiation and conductive noise within the limits shown below.
Page 41: Dc Power Requirements
6.2 DC power requirements Connection to the product should be made in isolated secondary circuits (SELV). The voltage specifica- tions are applied at the power connector of the drive. Item Requirements Notes Nominal Supply +5 Volt dc Supply Voltage –0.3 Volt to 6.0 Volt Power Supply Ripple (0–20 MHz) 100 mV p-p max Tolerance...
Page 42: Power Consumption Efficiency
6.2.1 Power consumption efficiency Capacity 48 GB 30 GB 20 GB 15 GB 12 GB 10 GB 7.5 GB 6 GB 5 GB Power Consumption 0.019 0.022 0.033 0.043 0.054 0.065 0.087 0.108 0.130 Efficiency (Watts/GB) Figure 24. Power consumption efficiency Note: Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/ Capacity (GB).
Page 43: Start Up Current
6.3 Start up Current 0.2 A/div 0.5 sec/div Figure 25. Typical current wave form at start up of IC25N048ATDA04-0 Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 44: Figure 26. Typical Current Wave Form At Start Up Of Ic25N030Atda04-0
0.2 A/div 0.5 sec/div Figure 26. Typical current wave form at start up of IC25N030ATDA04-0 0.2 A/div 0.5 sec/div Figure 27. Typical current wave form at start up of IC25N015ATDA04-0 Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 45: Reliability
6.4 Reliability 6.4.1 Data reliability ! Probability of not recovering data is 1 in 10 bits read ! ECC implementation On-the-fly correction performed as a part of read channel function recovers up to 15 symbols of error in 1 sector (1 symbol is 8 bits). 6.4.2 Failure prediction (S.M.A.R.T.) The drive supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function.
Page 46: Preventive Maintenance
6.4.5 Preventive maintenance None. 6.4.6 Load/unload The product supports a minimum of 300,000 normal load/unloads. Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code. Specifically, unloading of the heads is invoked by the following commands: ! Hard reset ! Standby ! Standby immediate...
Page 47: Travelstar 48Gh, 30Gn & 15Gn Hard Disk Drive Specifications
Simple power cycling of IC25XXXXATDAxx-x invokes the emergency unload mechanism and subjects the HDD to nontypical mechanical stress. Power cycling testing may be required to test the boot-up function of the system. In this case IBM recommends that the power-off portion of the cycle contain the sequence specified in Section 6.4.6.2, "Required Power-Off Sequence"...
Page 48: Mechanical Specifications
6.5 Mechanical specifications 6.5.1 Physical dimensions and weight The following table gives the dimensions for the 2.5 inch hard disk drive form factor. Model Height (mm) Width (mm) Length (mm) Weight (gram) 48 GB model 12.5±0.2 69.85±0.25 100.2±0.25 155 Max. 30 GB and 20 GB models 9.5±0.2 69.85±0.25...
Page 49: Connector And Jumper Description
Figure 30. Mounting hole locations for the 48 GB model 6.5.3 Connector and jumper description A jumper is used to designate the drive address as either master or slave. The jumper setting method is described in Section 7.10, "Drive Address Setting" on page 62. Connector specifications are included in Section 7.0, "Electrical interface specifications"...
Page 50: Load/Unload Mechanism
The user must use appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation. 6.5.5 Load/unload mechanism The head load/unload mechanism is provided to protect the disk data during shipping, movement, or storage.
Page 51: Vibration And Shock
6.6 Vibration and shock All vibration and shock measurements in this section are for hard disk drives without mounting attach- ments for the systems. The input level shall be applied to the normal drive mounting points. Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four mounting holes.
Page 52: Nonoperating Vibration
6.6.2 Nonoperating vibration The disk drive withstands the following vibration levels without any loss or permanent damage. 6.6.2.1 Random vibration The test consists of a random vibration applied in each of three mutually perpendicular axes with the time duration of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation envir- onment are shown below.
Page 53: Figure 35. Nonoperating Shock
6.6.4 Nonoperating shock The drive withstands the following half-sine shock pulse without any data loss or permanent damage. Model Duration of 1 ms Duration of 11 ms 48 GB model 700 G 120 G All other models 800 G 120 G Figure 35.
Page 54: Nonoperating Shock 6.7 Acoustics
6.7 Acoustics 6.7.1 Sound power level The criteria of A-weighted sound power level are described below. Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. The drives are to meet this requirement in both board down orientations.
Page 55: Discrete Tone Penalty
6.7.2 Discrete tone penalty Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only when determining compliance: Lwt(spec) = Lw + 0.1Pt + 0.3 < 4.0 (Bels) where Lw = A-weighted sound power level Pt = Value of desecrate tone penalty = dLt –...
Page 56: Identification Labels
6.8 Identification labels The following labels are affixed to every drive: A label is placed on the top of the HDA containing the statement "Made by IBM" or equivalent, Part No., EC No. and FRU No. A bar code label placed on the disk drive based on user request. The location on the drive is to be designated in the drawing provided by the user.
Page 57: Safety
6.10 Safety 6.10.1 UL and CSA approval The product is qualified per UL (Underwriters Labratory) 1950 Third Edition and CAN/CSA C22.2 No.950-M95 Third Edition, for the use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA monogram for CSA certification appears on the drive.
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Page 59: Electrical Interface Specifications
7.0 Electrical interface specifications 7.1 Cabling The maximum cable length from the host system to the hard disk drive shall not exceed 18 inches. 7.2 Interface connector The signal connector for AT attachment is designed to mate with the 50 pin plug specified in Annex A, Connectors and Cable Assembly, of the ATA/ATAPI-5 document.
Page 60: Signal Definitions
7.3 Signal definitions The pin assignments of interface signals are listed as follows: SIGNAL Type SIGNAL Type RESET- DD07 3–state DD08 3–state DD06 3–state DD09 3–state DD05 3–state DD10 3–state DD04 3–state DD11 3–state DD03 3–state DD12 3–state DD02 3–state DD13 3–state DD01...
Page 61: Figure 39. Special Signal Definitions For Ultra Dma
Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- Figure 39. Special signal definitions for Ultra DMA Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 62: Signal Descriptions
7.4 Signal descriptions DD00–DD15 A 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00–15, are used for data transfer. These are 3-state lines with 24 mA current sink capability. DA00–DA02 These are addresses used to select the individual register in the HDD.
Page 63 Following a Power On Reset, software reset, or RESET-, drive 1 shall negate PDIAG- within 1 ms (to indicate to device 0 that it is busy). Drive 1 shall then assert PDIAG- within 30 seconds to indicate that it is no longer busy and is able to provide status. Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate PDIAG- within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics.
Page 64 HSTROBE (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The signal HSTROBE is the data out strobe signal from the host for Ultra DMA data out transfers. Both the rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling HSTROBE to effect a pause in Ultra DMA data out transfers.
Page 65: Interface Logic Signal Levels
7.5 Interface logic signal levels The interface logic signals have the following electrical specifications: Inputs Input High Voltage 2.0 V min./5.5 V max. Input Low Voltage –0.5 V min./0.8 V max. Outputs: Output High Voltage 2.4 V min. Output Low Voltage 0.5 V max.
Page 66: Pio Timings
7.7 PIO timings The PIO cycle timings meet Mode 4 of the ATA-5 description. CS(1:0)- DA(2:0) DIOR-, DIOW- Write data DD(15:0) Read data DD(15:0) t7(*) t8(*) IOCS16-(*) IORDY (*) Up to ATA-2 (mode-0,1,2) PARAMETER DESCRIPTION MIN (ns) MAX. (ns) Cycle time –...
Page 67: Multiword Dma Timings
Multiword DMA timings The Multiword DMA timings meet Mode 2 of the ATA-5 description. DMARQ tLR/tLW DMACK- tKR/tKW DIOR-/DIOW- READ DD(15:0) WRITE DD(15:0) PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time – DIOR-/DIOW- asserted pulse width – DIOR- data access –...
Page 68: Ultra Dma Timings
7.9 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, 3, 4, and 5 of the Ultra DMA Protocol. 7.9.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC DSTROBE tZAD DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxx...
Page 69: Host Pausing Read Dma
7.9.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) DSTROBE to HDMARDY- –...
Page 70: Host Terminating Read Dma
7.9.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxxxxxxxxxxxxxxxxx xxx RD Data xxxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns)
Page 71: Device Terminating Read Dma
7.9.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns)
Page 72: Initiating Write Dma
7.9.5 Initiating Write DMA DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tCYC tCYC tACK HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns)
Page 73: Device Pausing Write Dma
7.9.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) HSTROBE to DDMARDY- time –...
Page 74: Device Terminating Write Dma
7.9.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns)
Page 75: Host Terminating Write Dma
7.9.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Page 76: Drive Address Setting
7.10 Drive address setting A jumper is available at the interface connector to determine the drive address. The set position of the jumper is as shown below. Using Cable Selection, the drive address depends on the condition of pin 28 of the AT interface cable. In the case when pin 28 is ground, or low, the drive is a Master.
Page 77: Addressing Of Hdd Registers
7.12 Addressing of HDD registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA00–02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time.
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Page 79: Part 2. Interface Specification
Part 2. Interface specification Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
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Page 81: General
8.0 General 8.1 Introduction This specification describes the host interface of the Travelstar 48GH, 30GN & 15GN (model numbers IC25xxxxATDAxx-x). The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-5), Revision 3 dated February 29, 2000, with certain limitations described in Section 9.0, "Deviations From Standard"...
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Page 83: Deviations From Standard
9.0 Deviations from standard The device conforms to the referenced specifications with deviations described below. The interface conforms to the Working Document of Information Technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-5), Revision 3 dated February 29, 2000, with deviation as follows: Standby Timer Standby timer is enabled by STANDBY command or IDLE command.
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Page 85: Registers
10.0 Registers Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-)) Data bus high imped Not used (*1) Control block registers Data bus high imped Not used Data bus high imped Not used Alternate Status Device Control Command block registers Data Data Error Register Features...
Page 86: Alternate Status Register
10.1 Alternate Status Register Alternate Status Register Figure 54. Alternate Status Register This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.
Page 87: Data Register
10.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide.
Page 88: Device/Head Register
10.7 Device/Head Register Device/Head Register Figure 56. Device/Head Register This register contains the device and head numbers. Bit Definitions Binary encoded address mode select. When L = 0 , addressing is by CHS mode. When L = 1, addressing is by LBA mode. Device.
Page 89: Error Register
10.8 Error Register Error Register IDNF ABRT TK0N Figure 57. Error Register This register contains the status from the last command executed by the device or a diagnostic code. At the completion of any command except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.
Page 90: Sector Number Register
10.11 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track. In LBA mode this register contains Bits 0–7. At the end of the command this register is updated to reflect the current LBA Bits 0–7.
Page 91: General Operation Descriptions
11.0 General operation descriptions 11.1 Reset response ATA has the following three types of resets: Power On Reset (POR) The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parametric, and sets default values.
Page 92: Figure 59. Reset Response Table
hard soft reset reset Aborting Host interface Aborting Device operation (*1) (*1) Initialization of hardware Internal diagnostic Starting or Spinning Up spindle motor (*6) Initialization of registers (*2) DASP- handshake PDIAG- handshake Reverting programmed parameters to (*3) default Ÿ Number of CHS (set by Initialize Device Parameters) Ÿ...
Page 93: Register Initialization
11.1.1 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status Alternate Status Figure 60.
Page 94: Diagnostic And Reset Considerations
11.2 Diagnostic and Reset considerations The Set Max password, the Set Max security mode and the Set Max unlock counter are not retained over a Power On Reset but are retained over a Hard Reset or Soft Reset. For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset, Hard Reset DASP- is read by Device 0 to determine if Device 1 is present.
Page 95: Power-Off Considerations
11.3 Power-off considerations 11.3.1 Load/Unload Load/Unload is a functional mechanism of the HDD. It is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the following commands. Command Response Standby UL -> Comp. Standby Immediate UL -> Comp. Sleep UL ->...
Page 96: Required Power-Off Sequence
11.3.3 Required power-off sequence Problems can occur on most HDDs when power is removed at an arbitrary time. Listed below are examples of such problems: Data loss from the write buffer. If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The sector contents are destroyed, and reading that sector results in a hard error.
Page 97: Power Management Features
LBA addressing mode Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0) being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1). Irre- spective of the logical CHS translation mode currently in effect, the LBA address of a given logical sector does not change.
Page 98: Standby/Sleep Command Completion Timing
The Idle and Idle Immediate commands move a device to idle mode immediately from the active or standby modes. The idle command also sets the standby timer count and starts the standby timer. The sleep command moves a device to sleep mode. The device's interface becomes inactive at the com- pletion of the sleep command.
Page 99: Initial Power Mode At Power On
Though the interface is inactive in sleep mode, the access to the interface registers and the validity of INTRQ is guaranteed for two seconds after the Sleep command is completed. After this period, the contents of interface registers may be lost. Since the contents of interface registers may be invalid, the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device.
Page 100: Low Power Idle Mode
11.6.3 Low Power Idle Mode Power consumption is 60–65% less than that of Performance Idle mode. The heads are unloaded on the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about 300 ms. 11.6.4 Transition Time The transition time is dynamically managed by users recent access pattern, instead of fixed times.
Page 101: Attribute Thresholds
degrading or fault condition existing. There is no implied linear reliability relationship corresponding to the numerical relationship between different attribute values for any particular attribute. 11.7.3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition.
Page 102: Security Mode
11.8.1 Security Mode Following security modes are provided. Device Locked Mode The device disables media access commands after power on. Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command. Device Unlocked Mode The device enables all commands.
Page 103: Figure 65. Initial Setting
11.8.5.2 User Password setting When a User Password is set, the device will automatically enter lock mode the next time the device is powered on. ( Ref.) < Setting password > < No setting password > Set Password with User Password Normal operation Normal operation Power off...
Page 104: Figure 66. Usual Operation
11.8.5.3 Operation from POR after user password is set When the Device Lock Function is enabled, the device rejects the media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media Access Command (*1) Command (*1)
Page 105: Figure 67. Password Lost
11.8.5.4 User Password lost If the User Password is forgotten and High level security is set, the system user can't access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
Page 106: Command Table
11.8.6 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Device Device Unlocked Device Command Locked Mode Mode Frozen Mode Check Power Mode Device Configuration RESTORE Device Configuration FREEZE LOCK Device Configuration IDENTIFY Devise Configuration SET...
Page 107: Figure 68. Command Table For Device Lock Operation (2 Of 2)
Device Device Device Command Locked Mode Unlocked Mode Frozen Mode Set Max UNLOCK Set Multiple Mode Sleep S.M.A.R.T. Disable Operations S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T. Enable Operations S.M.A.R.T. Execute Off-line Immediate S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Return Status S.M.A.R.T.
Page 108: Protected Area Function
11.9 Protected Area Function Protected Area Function is to provide the 'protected area' which cannot be accessed via conventional methods. This 'protected area' is used to contain critical system data such as BIOS or system management information. The contents of the entire system main memory may also be dumped into the 'protected area' to resume after a system power off.
Page 109: Set Max Security Extension Commands
Change maximum LBA using Set Max ADDRESS command to 0FBFFFh with nonvolatile option. From this point, the protected area cannot be accessed until next Set Max ADDRESS command is issued. Any BIOS, device driver, or application software accesses the HDD as if it is a 528 MB device because the device behaves like a 528 MB device.
Page 110: Figure 70. Set Max Security Mode Transition
The Set Max FREEZE LOCK command allows the host to disable the SET MAX commands (including Set Max UNLOCK) until the next power cycle. When this command is accepted the device is in the Set Max Frozen mode. The Set Max password, the Set Max security mode and the unlock counter do not persist over a power cycle but persist over a hardware or software reset.
Page 111: Address Offset Feature (Vendor Specific)
11.10 Address Offset Feature (vendor specific) Computer systems perform initial code loading (booting) by reading from a predefined address on a disk drive. To allow an alternate bootable operating system to exist in a reserved area on a disk drive this feature provides a Set Features function to temporarily offset the drive address space.
Page 112: Identify Device Data
11.10.2 Identify Device Data Identify Device data, word 83, bit 7 indicates that the device supports the Address Offset Feature. Identify Device data, word 86, bit 7 indicates that the device is in Address Offset mode. 11.10.3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error, even if the access protection is removed by a Set Max Address command.
Page 113: Seek Overlap
11.11 Seek Overlap The drive provides accurate seek time measurement method. The seek command is usually used to measure the device seek time by accumulating execution time for a number of seek commands. With typical implementation of the seek command, this measurement must include the device and host com- mand overhead.
Page 114: Write Cache Function
11.12 Write Cache function Write cache is a performance enhancement whereby the device reports completion of the write command (Write Sectors and Write Multiple) to the host as soon as the device has received all of the data in its buffer.
Page 115: Reassign Function
11.14 Reassign Function The Reassign Function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. The one entry can register 256 consecutive sectors maximum. This reassignment information is registered internally, and the information is available right after completing the reassign function.
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Page 117: Command Protocol
12.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.
Page 118 e. The host reads one sector (or block) of data via the Data Register. f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b.
Page 119: Data Out Commands
12.2 Data Out commands The following are examples of Data Out commands: Device Configuration Set Format Track Security Disable Password Security Erase Unit Security Set Password Security Unlock Set Max SET PASSWORD Set Max UNLOCK S.M.A.R.T. Write log sector Write Buffer Write Long Write Multiple Write Sectors...
Page 120 f. The device clears the interrupt in response to the Status Register being read. The Write Multiple command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt. If the device detects an invalid parameter, then it will abort the command by setting BSY = 0, ERR = 1, ABT = 1, and interrupting the host.
Page 121: Nondata Commands
12.3 Nondata commands The following are examples of Nondata commands: ! Check Power Mode ! Device Configuration FREEZE LOCK ! Device Configuration RESTORE ! Enable/Disable Delayed Write ! Execute Device Diagnostic ! Flush Cache ! Format Unit ! Idle ! Idle Immediate ! Initialize Device Parameters ! Read Native Max ADDRESS ! Read Verify Sectors...
Page 122: Dma Data Transfer Commands
12.4 DMA Data Transfer commands These commands are ! Identify Device DMA ! Read DMA ! Write DMA Data transfers using DMA commands differ in two ways from PIO transfers: ! Data transfers are performed using the Slave DMA channel ! No intermediate sector interrupts are issued on multisector commands Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands.
Page 123: Command Descriptions
13.0 Command descriptions Code Binary Code Bit Protocol Command (Hex) 7 6 5 4 3 2 1 0 Check Power Mode 1 1 1 0 0 1 0 1 Check Power Mode* 1 0 0 1 1 0 0 0 Device Configuration RESTORE 1 0 1 0 0 0 0 1 Device Configuration FREEZE LOCK...
Page 124: Figure 73. Command Set (2 Of 2)
Code Binary Code Bit Protocol Command (Hex) 7 6 5 4 3 2 1 0 Set Max LOCK 1 1 1 1 1 0 0 1 Set Max SET PASSWORD 1 1 1 1 1 0 0 1 Set Max UNLOCK 1 1 1 1 1 0 0 1 Set Multiple Mode 1 1 0 0 0 1 1 0...
Page 125: Figure 74. Command Set (Subcommand)
Command Feature Command (Subcommand) Code Register (Hex) (Hex) (Delayed Write Function) Enable Delayed Write function Disable Delayed Write function (S.M.A.R.T Function) S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T. Save Attribute Values S.M.A.R.T. Execute Off-line Immediate S.M.A.R.T.
Page 126 The following symbols are used in the command descriptions: Output Registers This indicates that the bit must be set to 0. Output Registers – continued This indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified.
Page 127: Check Power Mode (E5H/98H)
13.1 Check Power Mode (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 128: Device Configuration Overlay (B1H)
13.2 Device Configuration Overlay (B1h) Command Block Output Registers Command Block Input Registers Register Register Data Data Feature Error ...See Below... Sector Count Sector Count Sector Sector Number Number Cylinder Low Cylinder Low Cylinder Cylinder High High Device/Head Device/Head Command Status ...See Below...
Page 129: Device Configuration Freeze Lock (Subcommand C1H)
13.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h) The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE commands are aborted by the device.
Page 130: Figure 78. Device Configuration Overlay Data Structure
ERROR INFORMATION EXAMPLE 2: If the device has enabled the Security feature set and if a user attempts to disable that feature, the device aborts that command and returns an error reason code as below. Cylinder high : 07h = word 7 is invalid Cylinder low : 03h = bit 3 is invalid...
Page 131: Figure 79. Dco Error Information Definition
Cylinder high invalid word location Cylinder low invalid bit location Sector count error reason code & description DCO feature is frozen Device is now Security Locked mode Device's feature is already modified with DCO User attempt to disable any feature enabled Device is now SET MAX Locked or Frozen mode Protected area is now established DCO is not supported...
Page 132: Enable/Disable Delayed Write (Fah: Vendor Specific)
13.3 Enable/Disable Delayed Write (FAh: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 133: Execute Device Diagnostic (90H)
13.4 Execute Device Diagnostic (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 134: Flush Cache (E7H)
13.5 Flush Cache (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 135: Format Track (50H: Vendor Specific)
13.6 Format Track (50h: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 136 In LBA mode this register specifies the current LBA address bits as 24–27 (L = 1). Error This indicates the Error Register. An Abort error (ABT = 1) will be returned under the following conditions: Ÿ The descriptor value does not match the certain value (except 00h). In LBA mode this command formats a single logical track including the specified LBA.
Page 137: Format Unit (F7H: Vendor Specific)
13.7 Format Unit (F7h: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 138 The execution time of this command is shown below: 48 GB model 52 min 30 GB model 38 min 20 GB model 24 min 15 GB model 20 min 12 GB model 16 min 10 GB model 14 min 7.5 GB model 10 min 6 GB model 8 min...
Page 139: Identify Device (Ech)
13.8 Identify Device (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 140: Figure 86. Identify Device Information (1 Of 7)
Word Content Description Drive 045AH Bit assignments classification 15(=0) 1=ATAPI device, 0=ATA device 14(=0) 1=format speed tolerance gap required 13(=0) 1=track offset option available 12(=0) 1=data strobe offset option available 11(=0) 1=rotational speed tolerance > 0.5% 10(=1) 1=disk transfer rate > 10 Mbps 9(=0) 1=disk transfer rate >...
Page 141: Figure 86. Identify Device Information (2 Of 7)
Word Content Description 0000H Capable of double word I/O, ‘0000’= cannot perform 0F00H Capabilities, bit assignments: 15-14(=0) Reserved 13(=0) Standby timer value are vendor specific 12(=0) Reserved 11(=1) IORDY Supported 10(=1) IORDY can be disabled 9(=1) Reserved 8(=0) Reserved 7–0(=0) Reserved 0000H Capabilities...
Page 142: Figure 86. Identify Device Information (3 Of 7)
Word Content Description 0003H Flow Control PIO Transfer Modes Supported 15- 8(=0) Reserved 7- 0(=3) Advanced PIO Transfer Modes Supported ‘11’ = PIO Mode 3 and 4 Supported 0078H ns, 16.6MB/s) 0078H Manufacturer’s Recommended Multiword DMA Transfer Cycle Time 15- 0(=78) Cycle time in nanoseconds(120ns, 16.6MB/s) 00F0H Minimum PIO Transfer Cycle Time Without Flow Control 15- 0(=F0) Cycle time in nanoseconds (240ns, 8.3MB/s)
Page 143: Figure 86. Identify Device Information (4 Of 7)
Word Content Description 49A8H Command set supported 15(=0) Always 14(=1) Always 13-12(=0) Reserved 11(=1) 1=Device Configuration Overlay command supported 10-9(=0) Reserved 8(=1) 1=SET MAX security extension supported 7(=1) 1=Address Offset feature supported 6(=0) 1=SET FEATURES subcommand required to spin-up 5(=1) 1=Power-Up In Standby feature set supported 4(=0) 1=Removable Media Status Notification Feature...
Page 144: Figure 86. Identify Device Information (5 Of 7)
Word Content Description 0XXXH Command set/feature enabled 15-12(=0) Reserved 11(=x) 1=Device Configuration Overlay supported 10-9(=0) 1=Reserved 8(=1) 1=Device Configuration Overlay supported 7(=X) 1=Address Offset mode enabled 6(=0) 1=SET FEATURES subcommand required to spin-up 5(=0) 1=Power-Up In Standby feature set has been enabled via the SET FEATURES command 4(=0) 1=Removable Media Status Notification Feature...
Page 145: Figure 86. Identify Device Information (6 Of 7)
Word Content Description XXXXH Hardware reset results 15-13 Device detected result 15(=0) Reserved 14(=1) Always 13(=X) 1=Device detected CBLID- above V 0=Device detected CBLID- below V 12- 8 Device 1 hardware reset result Device 0 clear these bits to 0 12(=0) Reserved 11(=X)
Page 146: Figure 86. Identify Device Information (7 Of 7)
Word Content Description 000XH Current Set Feature Option. Bit assignments 15-4(=0) Reserved 3(=X) 1=Auto reassign enabled 2(=X) 1=Reverting enabled 1(=X) 1=Read Look-ahead enabled 0(=X) 1=Write Cache enabled XXXXH Reserved 000XH Initial Power Mode Selection. Bit assignments 15-2(=0) Reserved 1(=1) Always 0(=X) Initial Power Mode 1=Standby, 0=Idle 132-254...
Page 147: Figure 87. Number Of Cylinders/Heads/Sectors By Model Number
IC25T048ATDA05-0 Number of cylinders 3FFFh Number of heads Buffer size 0E1Ch(=1,806KB) Number of user addressable sectors 596A690h IC25N030ATDA04-0 Number of cylinders 3FFFh Number of heads Buffer size 0E1Ch(=1,806KB) Number of user addressable sectors 37E3E40h IC25N020ATDA04-0 Number of cylinders 3FFFh Number of heads Buffer size 0E1Ch(=1,806k) Number of user addressable sectors...
Page 148: Identify Device Dma (Eeh)
13.9 Identify Device DMA (EEh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 149: Idle (E3H/97H)
13.10 Idle (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - - Error...
Page 150: Idle Immediate (E1H/95H)
13.11 Idle Immediate (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 151: Initialize Device Parameters (91H)
13.12 Initialize Device Parameters (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 152: Read Buffer (E4H)
13.13 Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 153: Read Dma (C8H/C9H)
13.14 Read DMA (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 154 This indicates the head number of the first sector to be transferred. (L = 0) In LBA mode this register specifies the LBA bits 24–27 to be transferred. (L = 1) This indicates the retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred.
Page 155: Read Long (22H/23H)
13.15 Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 156 This indicates the retry bit. If it is set to one then retries are disabled. Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred. Sector Number This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7.
Page 157: Read Multiple (C4H)
13.16 Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 158 Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred. This number is zero unless an unrecoverable error occurs. Sector Number This indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7.
Page 159: Read Native Max Address (F8H)
13.17 Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 160 In LBA mode this register contains the native max LBA bits 24–27. (L = 1) In the CHS mode this register contains the native maximum head number. (L = 0) Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the device.
Page 161: Read Sectors (20H/21H)
13.18 Read Sectors (20h/21h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 162 Input Parameters From The Device Sector Count This is the number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. Sector Number This is the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7.
Page 163: Read Verify Sectors (40H/41H)
13.19 Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 164 This is the head number of the first sector to be transferred. (L = 0) In LBA mode this register contains the LBA bits 24–27. (L = 1) This is the retry bit. If it is set to one then retries are disabled. Input Parameters From The Device Sector Count This is the number of requested sectors not verified.
Page 165: Recalibrate (1Xh)
13.20 Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - - Error...
Page 166: Security Disable Password (F6H)
13.21 Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 167: Security Erase Prepare (F3H)
13.22 Security Erase Prepare (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 168: Security Erase Unit (F4H)
13.23 Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 169 Identifier Zero indicates that the device should check the supplied password against the user password stored internally. One indicates that the device should check the given pass- word against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).
Page 170: Security Freeze Lock (F5H)
13.24 Security Freeze Lock (F5h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 171: Security Set Password (F1H)
13.25 Security Set Password (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 172: Figure 107. Security Set Password Information
Word Description Control Word bit 0 : Identifier (1- Master, 0- User) bit 1-7 : Reserved bit 8 : Security level (1- Maximum, 0- High) bit 9-15 : Reserved 01-16 Password ( 32 bytes ) Master Password Revision Code 17-18 (valid if Word 0 bit 0 = 1) 19-255 Reserved...
Page 173: Security Unlock (F2H)
13.26 Security Unlock (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 174: Figure 109. Security Unlock Information
Word Description Control Word bit 0 : Identifier (1- Master, 0- User) bit 1-15 : Reserved 01-16 Password ( 32 bytes ) 17-255 Reserved Figure 109. Security Unlock information Identifier A zero indicates that the device regards Password as the User Password. A one indicates that the device regards Password as the Master Password.
Page 175: Seek (7Xh)
13.27 Seek (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - - Error...
Page 176: Sense Condition (F0H: Vendor Specific)
13.28 Sense Condition (F0h: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 177: Set Features (Efh)
13.29 Set Features (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature V V V V V V V V...
Page 178 Output Parameters To The Device Feature Destination code for this command. Enable write cache (See note 2) Set transfer mode based on value in sector count register Enable Advanced Power Management Enable Address Offset mode 40 bytes of ECC apply on Read Long/Write Long commands Disable read look-ahead feature Disable reverting to power on defaults Disable write cache...
Page 179: Set Max Address (F9H)
13.30 Set Max ADDRESS (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 180 Output Parameters To The Device Feature Destination code for this command SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK When the Set Max ADDRESS command is executed, this register is ignored. This indicates the option bit for selection whether nonvolatile or volatile. B = 0 is the volatile condition.
Page 181: Set Multiple (C6H)
13.31 Set Multiple (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 182: Sleep (E6H/99H)
13.32 Sleep (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - - Error...
Page 183: Function Set (B0H)
13.33 S.M.A.R.T. Function Set (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 184: Function Subcommands
S.M.A.R.T. Enable Operations S.M.A.R.T. Disable Operations S.M.A.R.T. Return Status S.M.A.R.T. Enable/Disable Automatic Off-line 13.33.1 S.M.A.R.T. Function Subcommands 13.33.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the S.M.A.R.T. Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register.
Page 185: Figure 117. Log Sector Addresses
13.33.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h) This subcommand causes the device to immediately initiate the set of activities that collect Attribute data in an off-line mode (off-line routine) or execute a self-test routine in either captive or off-line mode. The Sector Number register shall be set to specify the operation to be executed.
Page 186 13.33.1.7 S.M.A.R.T. Write Log Sector (subcommand D6h) This command writes 512 bytes of data to the specified log sector. The 512 bytes of data are transferred at a command and the Sector Count value shall be set to one. The Sector Number must be set to specify the "log sector address"...
Page 187 13.33.1.11 S.M.A.R.T. Enable/Disable Automatic Off-Line (subcommand DBh) This subcommand enables and disables the optional feature that cause the device to perform the set of off-line data collection activities that automatically collect attribute data in an off-line mode and then save this data to the device's nonvolatile memory.
Page 188: Device Attributes Data Structure
13.33.2 Device Attributes Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures follow the ATA/ATAPI-5 specification for byte ordering, namely that the least significant byte occupies the lowest numbered byte address location in the field.
Page 189: Figure 119. Individual Attribute Data Structure
13.33.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Byte Offset Value Attribute ID Number (01h to FFh) binary Status Flags bit flags Bit 0 Pre-Failure/Advisory Bit 1...
Page 190: Figure 120. Status Flag Definitions
Spin Retry Count Device Power Cycle Count Gsense Error Rate Power Off Retract Count Load/Unload Cycle Count Device Temperature Reallocation Event Count Current Pending Sector Count Off-Line Scan Uncorrectable Sector Count Ultra DMA CRC Error Count Status Flag definitions: Flag Name Definition Pre-Failure/ If bit = 0, an Attribute Value less than or equal...
Page 191 13.33.2.3 Off-Line Data Collection Status The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates an Automatic Off-line Data Collection Status. Bit 7 Automatic Off-line Data Collection Status Automatic Off-line Data Collection is disabled. Automatic Off-line Data Collection is enabled.
Page 192 13.33.2.6 Current segment pointer This byte is a counter indicating the next segment to execute as an off-line data collection activity. Because the number of segments is 1, 01h is always returned in this field. 13.33.2.7 Off-line data collection capability Definition The Execute Off-line Immediate implemented bit S.M.A.R.T.
Page 193: Device Attribute Thresholds Data Structure
13.33.2.9 Error logging capability Definition 7–1 Reserved (0) The Error Logging support bit If bit = 1, the device supports the Error Logging 13.33.2.10 Self-test failure check point This byte indicates the section of self-test where the device detected a failure. 13.33.2.11 Self-test completion time These bytes are the minimum time in minutes to complete the self-test.
Page 194: Figure 122. Individual Threshold Data Structure
13.33.3.2 Individual Thresholds Data Structure The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute Thresholds Data Structure. Attribute entries in the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure. Description Byte Offset...
Page 195: Error Log Sector
13.33.4 S.M.A.R.T. error log sector The following defines the 512 bytes that make up the S.M.A.R.T. error log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI-5 specifications for byte ordering. Description Byte Offset S.M.A.R.T. error log version Error log pointer 1st error log data structure 2nd error log data structure...
Page 196: Figure 124. Error Log Data Structure
13.33.4.4 Error log data structure The data format of each error log structure is shown below. Description Byte Offset 1st error log data structure 2nd error log data structure 3rd error log data structure 4th error log data structure 5th error log data structure Error data structure Figure 124.
Page 197: Figure 126. Error Data Structure
13.33.4.4.1 Error data structure Data format of error data structure is shown below. Description Byte Offset Reserved Error register Sector count register Sector number register Cylinder Low register Cylinder High register Device/Head register Status register Extended error data (vendor specific) State Life time stamp (hours) Figure 126.
Page 198: Self-Test Log Data Structure
13.33.5 Self-test log data structure The following defines the 512 bytes that make up the Self-test log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI-5 specifications for byte ordering. Description Byte Offset Data structure revision Self-test number n*18h+02h Self-test execution status n*18h+03h...
Page 199: Error Reporting
13.33.6 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Status Error Error condition Register Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers.
Page 200: Standby (E2H/96H)
13.34 Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - - Error...
Page 201: Standby Immediate (E0H/94H)
13.35 Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 202: Write Buffer (E8H)
13.36 Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature - - - - - - - -...
Page 203: Write Dma (Cah/Cbh)
13.37 Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
Page 204 This indicates the head number of the first sector to be transferred. (L = 0) In LBA mode this register contains the LBA bits 24–27. (L = 1) Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred. The Sector Count will be zero unless an unrecoverable error occurs.
Page 205: Write Long (32H/33H)
13.38 Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
Page 206 This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains the LBA bits 24–27. (L = 1) The retry bit. If the retry bit is set to one, then retries are disabled. Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred.
Page 207: Write Multiple (C5H)
13.39 Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
Page 208 Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred. The Sector Count will be zero, unless an unrecoverable error occurs. Sector NumberThis indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains current the LBA bits 0–7.
Page 209: Write Sectors (30H/31H)
13.40 Write Sectors (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
Page 210: Write Verify (3Ch: Vendor Specific)
Input Parameters From The Device Sector Count This indicates the number of requested sectors not transferred. The Sector Count will be zero unless an unrecoverable error occurs. Sector Number This indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7.
Page 211: Time-Out Values
14.0 Time-out values The timing of BSY and DRQ in Status Register are shown in the table below. INTERVAL START STOP TIME-OUT Power On Device Busy Power On Status Register 400 ns After Power On BSY=1 Device Ready Power On Status Register 31 sec After Power On...
Page 212 We recommend that the host system execute Soft reset and then retry to issue the command if the host system time-out would occur for the device. Note 1. For SECURITY ERASE UNIT command, the execution time is referred to 13.23, "Security Erase Unit (F4h)"...
Page 213: Appendix
15.0 Appendix 15.1 Commands Support Coverage The following table is provided to facilitate the understanding of command support coverage of the drive compared to the ATA-5 defined command set. The column entitled "Implementation for Travelstar 48 GH, 30 GN & 15 GN" shows the capability of the drive for those commands. Command Command Name Implementation...
Page 214: Figure 137. Command Coverage (2 Of 2)
Command Command Name Implementation ATA-5 Command Type Code for Travelstar 48GH,30GN & 15GN WRITE DMA (w/ retry) Mandatory WRITE DMA (w/o retry) obsoleted WRITE DMA QUEUED Optional CFA WRITE MULTIPLE W/O ERASE Optional (7) GET MEDIA STATUS Optional (7) MEDIA LOCK Optional (7) MEDIA UNLOCK Optional (7)
Page 215: Set Features Command Support Coverage
15.2 SET FEATURES Command Support Coverage The following table provides a list of Feature Registers and Feature Names as well as a column titled "Implementation for Travelstar 48GH, 30GN & 15GN" which indicates whether the drive has the capability of executing the command in comparison to the ATA/ATAPI-5 defined command set. For details of operation, refer to Section 13.29, "Set Features (EFh)"...
Page 216 This page intentionally left blank. Travelstar 48GH, 30GN & 15GN hard disk drive specifications...
Page 217: Index
Index S.M.A.R.T. Function Set (B0h), 169 Security Disable Password (F6h), 152 ABLE-3, 85 Security Erase Prepare (F3h), 153 ABRT, 75 Security Erase Unit (F4h), 154 ABT, 75 Security Freeze Lock (F5h), 156 Active Idle mode, 85 Security Set Password (F1h), 157 Adaptive Power Management Feature Security Unlock (F2h), 159 Low Power Idle Mode, 86...
Page 218 Error Register PIO timings, 52 Diagnostic Codes, 79 Power management, 83 Example for operation (In LBA Mode), 94 Power Management Feature Execute Device Diagnostic, 119 Initial Power Mode at Power On, 85 Interface Capability for Power Modes, 84 Power Management Commands, 83 Power mode, 83 Flush Cache, 120 Standby timer, 84...
Page 219 S.M.A.R.T. operation with power management SMART Enable/Disable Attribute Autosave, 107 modes, 87 SMART Execute Off-line Immediate, 107 S.M.A.R.T. Capability, 178 SMART Read Attribute Thresholds, 103 S.M.A.R.T. function, 86 SMART Read Attribute Values, 103 Attribute thresholds, 87 SMART Return Status, 107 Attribute values, 86 SMART Save Attribute Values, 107 Attributes, 86...
Page 220 IBM representative. Data subject to change without notice. References in this publication to IBM products, programs, or services do not imply that IBM intends to make them available in all countries in which IBM operates. Document #S07N-7909-09 Publication #1530...

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IBM IC25N020ATDA04 - Travelstar 20 GB Hard Drive Specifications

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1 Introduction

2 General Features

Part 1. Functional Specification

3 Fixed Disk Subsystem Description

4 Fixed Disk Characteristics

5 Data Integrity

6 Specification

7 Electrical Interface Specifications

Part 2. Interface Specification

8 General

9 Deviations from Standard

10 Registers

11 General Operation Descriptions

12 Command Protocol

13 Command Descriptions

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