Hitachi 7K100 - Travelstar - Hard Drive Specifications
  1. Manuals
  2. Brands
  3. Hitachi Manuals
  4. Storage
  5. Travelstar 7K100
  6. Specifications

Hitachi 7K100 - Travelstar - Hard Drive Specifications

2.5 inch ata/ide hard disk drive
Hide thumbs Also See for 7K100 - Travelstar - Hard Drive:
Table of Contents

Advertisement

Quick Links

Hard Disk Drive Specification
Hitachi Travelstar 7K100
2.5 inch ATA/IDE hard disk drive
Model:
HTS721010G9AT00
HTS721080G9AT00
HTS721060G9AT00
Revision 1.3
13 July 2006

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the 7K100 - Travelstar - Hard Drive and is the answer not in the manual?

Questions and answers

Related Manuals for Hitachi 7K100 - Travelstar - Hard Drive

Summary of Contents for Hitachi 7K100 - Travelstar - Hard Drive

  • Page 1 Hard Disk Drive Specification Hitachi Travelstar 7K100 2.5 inch ATA/IDE hard disk drive Model: HTS721010G9AT00 HTS721080G9AT00 HTS721060G9AT00 Revision 1.3 13 July 2006...
  • Page 3 Hard Disk Drive Specification Travelstar 7K100 2.5 inch ATA/IDE hard disk drive Model: HTS721010G9AT00 HTS721080G9AT00 HTS721060G9AT00 Revision 1.3 13 July 2006...
  • Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your country.

  • Page 5: Table Of Contents

    Table of Contents 1.0 General.......................1 1.1 Introduction.....................1 1.2 References....................1 1.3 Abbreviations..................1 1.4 Caution....................3 1.5 Drive handling precautions ..............3 2.0 Outline of the drive ...................5 3.0 Fixed-disk subsystem description..............9 3.1 Control electronics ..................9 3.2 Head disk assembly data.................9 4.0 Drive characteristics ..................11 4.1 Formatted capacity..................11 4.2 Data sheet....................11 4.3 Cylinder allocation..................12...
  • Page 6 6.3.4 Service life and usage condition ............25 6.3.5 Preventive maintenance ..............25 6.3.6 Load/unload ...................26 6.4 Mechanical specifications...............28 6.4.1 Physical dimensions and weight ............28 6.4.2 Mounting hole locations ..............28 6.4.3 Connector and jumper description ..........28 6.4.4 Mounting orientation ..............29 6.4.5 Load/unload mechanism ..............29 6.5 Vibration and shock ................30 6.5.1 Operating vibration ................30 6.5.2 Nonoperating vibration ..............31...
  • Page 7 7.9.7 Device Terminating Write DMA ...........49 7.9.8 Host Terminating Write DMA............50 7.10 Drive address setting................51 7.11 Addressing of HDD registers..............52 8.0 General.......................55 8.1 Introduction.....................55 8.2 Terminology....................55 9.0 Deviations from standard.................57 10.0 Register ......................59 10.1 Alternate Status Register ..............60 10.2 Command Register ................60 10.3 Data Register..................60 10.4 Device Control Register................61 10.5 Drive Address Register .................61...
  • Page 8 11.8 S.M.A.R.T. Function ................73 11.8.1 Attributes ..................73 11.8.2 Attribute values................73 11.8.3 Attribute thresholds..............73 11.8.4 Threshold exceeded condition .............73 11.8.5 S.M.A.R.T. commands ..............73 11.8.6 S.M.A.R.T. operation with power management modes....74 11.9 Security Mode Feature Set..............74 11.9.1 Security mode ................74 11.9.2 Security level ................74 11.9.3 Password ..................75 11.9.4 Master Password Revision Code ..........75 11.9.5 Command table ................78...
  • Page 9 13.12 Read Buffer (E4h)................118 13.13 Read DMA (C8h/C9h)................119 13.14 Read DMA EXT (25h) ...............121 13.15 Read Log Ext (2Fh) ................123 13.15.1 General Purpose Log Directory ..........124 13.15.2 Extended Comprehensive SMART Error Log......125 13.15.3 Extended Self-test log sector .............127 13.16 Read Long (22h/23h) ................129 13.17 Read Multiple (C4h) ................131 13.18 Read Multiple EXT (29h) ..............133 13.19 Read Native Max ADDRESS (F8h) ...........134...
  • Page 10 13.47 Write Multiple (C5h) ................190 13.48 Write Multiple EXT (39h) ..............191 13.49 Write Sectors (30h/31h)..............193 13.50 Write Sectors(s) EXT (34h) ..............195 13.51 Write Verify (3Ch: vendor specific) ...........196 14.0 Time-out values ....................197 15.0 Appendix......................199 15.1 Commands Support Coverage ..............199 15.2 SET FEATURES Commands Support Coverage .........201 15.3 Changes from the Travelstar 5K100 .............202...
  • Page 11 List of Tables Table 1. Formatted capacities ..................11 Table 2. Data sheet.....................11 Table 3. Cylinder allocation..................12 Table 4. Performance characteristics .................13 Table 5. Mechanical positioning performance ............14 Table 6. Full stroke seek time ..................14 Table 7. Single track seek time ..................15 Table 8.
  • Page 12 Table 42. Device Head/Register ................62 Table 43. Error Register.....................62 Table 44. Status Register ...................64 Table 45. Reset response table...................65 Table 46. Default Register Values ................66 Table 47. Diagnostic codes ..................66 Table 48. Interpretation of Device 0 Error..............67 Table 49. Device behavior by ATA command ............68 Table 50.
  • Page 13 Table 88. Read Long (22h/23h) .................129 Table 89. Read Multiple (C4h) ..................131 Table 90. Read Multiple EXT (29h) ................133 Table 91. Read Native Max ADDRESS (F8h) ............134 Table 92. Read Native Max ADDRESS EXT (27h) ..........135 Table 93. Read Sectors (20h/21h)................136 Table 94.
  • Page 14 Table 134. Write Multiple EXT (39h) ...............191 Table 135. Write Sectors Command (30h/31h) ............193 Table 136. Write Sector(s) EXT Command (34h).............195 Table 137. Time-out values ..................197...

  • Page 15: General

    1.0 General 1.1 Introduction This document describes the specifications of the Travelstar 7K100, a 2.5-inch hard disk drive with ATA/IDE inter- face. Drive name Model Number Capacity (GB) Height (mm) Rotation speed (rpm) Travelstar 7K100-100 HTS721010G9AT00 7200 Travelstar 7K100-80 HTS721080G9AT00 7200 Travelstar 7K100-60 HTS721060G9AT00...
  • Page 16 1,000,000,000 bits 1,000,000,000 bytes ground hexadecimal hard disk drive Hertz Input integrated lead suspension Input/Output International Standards Organization 1,000 bytes Kbpi 1000 bits per inch kgf-cm kilogram (force)-centimeter kilohertz logical block addressing unit of A-weighted sound power meter maximum 1,000,000 bytes Mbps 1,000,000 bits per second megahertz...

  • Page 17: Caution

    SELV secondary low voltage S.M.A.R.TSelf-Monitoring, Analysis, and Reporting Technology tracks per inch track transistor-transistor logic Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.4 Caution • Do not apply force to the top cover (See figure below). •...
  • Page 18 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 19: Outline Of The Drive

    2.0 Outline of the drive • 2.5 inch, 9.5-mm height • Formatted capacity of 100 GB, 80 GB, 60 GB • 512 bytes/sector • AT Interface (Enhanced IDE) conforming to ATA/ATAPI-6 • Integrated controller • No-ID recording format • Coding : 100/106 •...
  • Page 20 Travelstar 7K100 Hard Disk Drive Specification...
  • Page 21 Part 1. Functional specification Travelstar 7K100 Hard Disk Drive Specification...
  • Page 22 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 23: Fixed-Disk Subsystem Description

    3.0 Fixed-disk subsystem description 3.1 Control electronics The control electronics works with the following functions: • AT Interface Protocol • Embedded Sector Servo • No-ID (TM) formatting • Multizone recording • Code: 100/106 • ECC On-The-Fly • Enhanced Adaptive Battery Life Extender 3.2 Head disk assembly data The following technologies are used in the drive: •...
  • Page 24 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 25: Drive Characteristics

    4.0 Drive characteristics 4.1 Formatted capacity Table 1: Formatted capacities HTS721010G9AT00 HTS721080G9AT00 HTS721060G9AT00 Physical Layout Bytes per sec- Sectors per 459-900 414-792 414-792 track (typical format) Number of heads Number of disks Logical Lay- Number of heads Number of Sectors/track Number of 16,383 16,383...

  • Page 26: Cylinder Allocation

    4.3 Cylinder allocation Each drive is formatted in the factory test by optimizing TPI/BPI combination. Typical data format is described below. Table 3: Cylinder allocation 50 GB/p Mid BIP-TPI format Zone Physical cylinders Sectors/Track Data Zone 0 0 - 1923 Data Zone 1 1924 - 4957 Data Zone 2...

  • Page 27: Performance Characteristics

    4.4 Performance characteristics Drive performance is characterized by the following parameters: • Command overhead • Mechanical head positioning Seek time Latency • Data transfer speed • Buffering operation (read ahead/write cache) Note: All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system.

  • Page 28: Mechanical Positioning

    4.4.2 Mechanical positioning 4.4.2.1 Average seek time (including settling) Table 5: Mechanical positioning performance Command type Typical (ms) Max (ms) Read Write “Typical” and “Max” are used throughout this document and are defined as follows: Typical Average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions.

  • Page 29: Table 7. Single Track Seek Time

    4.4.2.3 Single track seek time (without command overhead, including settling) Table 7: Single track seek time Command type Typical (ms) Max (ms) Read Write Single track seek is measured as the average of one (1) single track seek from every track in both directions (inward and outward).

  • Page 30: Operating Modes

    4.4.3 Operating modes 4.4.3.1 Description of operating modes Table 10: Description of operating modes Operating mode Description Start up time period from spindle stop or power down. Spin-up Seek operation mode Seek Write operation mode Write Read operation mode Read The device is capable of responding immediately to idle media access requests.

  • Page 31: Data Integrity

    5.0 Data integrity 5.1 Data loss at power off • Data loss will not be caused by a power off during any operation except the write operation. • A power off during a write operation causes the loss of any received or resident data that has not been written onto the disk media.

  • Page 32: Write Safety

    5.4 WRITE safety The drive ensures that the data is written into the disk media properly. The conditions listed below are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked. •...

  • Page 33: Ecc

    5.8 ECC The 10 bit 40 symbol non interleaved ECC processor provides user data verification and correction capa- bility. The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC. The other 34 symbols are Read Solomon ECC. Hardware logic corrects up to 16 symbols(20 bytes) errors on- the-fly.
  • Page 34 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 35: Specification

    6.0 Specification 6.1 Environment 6.1.1 Temperature and humidity Table 12: Environmental condition Operating conditions Temperature 5 to 55ºC (See note below) Relative humidity 8 to 90%, non-condensing Maximum wet bulb temperature 29.4ºC, non-condensing Maximum temperature gradient 20ºC/hour Altitude –300 to 3,048 m (10,000 ft) Non-operating conditions Temperature –40 to 65ºC...

  • Page 36: Table 13. Limits Of Temperature And Humidity

    Table 13: Limits of temperature and humidity Specification (Environment) 41'C/95% 31'C/90% WetBulb 40'C WetBulb29.4'C Non Operating Operating 65'C/23% 55'C/15% Temperature (degC) 6.1.1.1 Corrosion test The drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50°C/90% RH (relative humidity) for one week followed by a temperature and humidity drop to 25°C/40%RH in 2 hours.

  • Page 37: Radiation Noise

    6.1.2 Radiation noise The drive shall work without degradation of the soft error rate under the following magnetic flux density limits at the enclosure surface. Table 14: Magnetic flux density limits Frequency (KHz) Limits (uT RMS) 0–60 61–100 101–200 201–400 6.1.3 Conductive noise The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA (p-p) is applied...

  • Page 38: Dc Power Requirements

    6.2 DC power requirements Connection to the product should be made in a safety extra low voltage (SELV) circuits. The voltage specifications are applied at the power connector of the drive. Table 15: DC power requirements Item Requirements Nominal supply +5Volt DC Supply voltage –0.3 Volt to 6.0 Volt...

  • Page 39: Reliability

    6.3 Reliability 6.3.1 Data Reliability • Probability of not recovering data is 1 in 10 bits read • ECC implementation On-the-fly correction performed as a part of read channel function recovers up to 20 symbols of error in one sector (1 symbol is 8 bits).

  • Page 40: Load/Unload

    In systems that use this drive consideration should be given to the design of the system power switch. Hitachi recommends that the switch operate under control of the BIOS rather than be hardwired. The same recom- mendation is made for cover-close switches. When a hardwired switch is turned off, emergency unload occurs, as...
  • Page 41 HDD to nontypical mechan- ical stress. Power cycling testing may be required to test the boot-up function of the system. In this case Hitachi recommends that the power-off portion of the cycle contain the sequence specified in Section 6.3.6.2, “Required Power-Off Sequence”...

  • Page 42: Mechanical Specifications

    6.4 Mechanical specifications 6.4.1 Physical dimensions and weight The following table lists the dimensions of the drive. Table 17: Physical dimensions and weight Height [mm] 9.5±0.2 Width [mm] 69.85±0.25 Length [mm] 100.2±0.25 Weight [grams - maximum] 115 Max 6.4.2 Mounting hole locations The mounting hole locations and size of the drive are shown below.

  • Page 43: Mounting Orientation

    Connector specifications are included in Section 7.2, “Interface connector” on page 35. 6.4.4 Mounting orientation The drive will operate in all axes (six directions) and will stay within the specified error rates when tilted ±5degrees from these positions. Performance and error rate will stay within specification limits if the drive is operated in the other permissible ori- entations from which it was formatted.

  • Page 44: Vibration And Shock

    6.5 Vibration and shock All vibration and shock measurements in this section are for drives without mounting attachments for systems. The input level shall be applied to the normal drive mounting points.Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four mounting holes.

  • Page 45: Nonoperating Vibration

    6.5.2 Nonoperating vibration The disk drive withstands the vibration levels described below without any loss or permanent damage. 6.5.2.1 Random vibration The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration of 15 minutes per axis.

  • Page 46: Acoustics

    The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a time. Input levels are measured on a base plate where the drive is attached with four screws 6.6 Acoustics 6.6.1 Sound power levels The criteria of A-weighted sound power level are described below.

  • Page 47: Identification Labels

    6.7 Identification labels The following labels are affixed to every drive: • A label which is placed on the top of the head disk assembly containing the statement "Made by Hitachi" or equivalent, part number, EC number, and FRU number.

  • Page 48: Safety

    6.9 Safety The drive complies with the safety standards of different countries as listed below. 6.9.1 UL and CSA approval The drive is qualified per UL (Underwriters Laboratory) 60950 Third Edition (2000) and CAN/CSA C22.2 No.60950-1 Third Edition, for use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition or the CSA certification is maintained for the product life.

  • Page 49: Electrical Interface Specification

    7.0 Electrical interface specification 7.1 Cabling The maximum cable length from the host system to the hard disk drive plus circuit pattern length in the host system shall not exceed 18 inches. 7.2 Interface connector The signal connector for AT attachment is designed to mate with Dupont part number 69764-044 or equivalent. The figure below and show the connector and pin location.

  • Page 50: Signal Definitions

    7.3 Signal definitions The pin assignments of interface signals are listed as follows:Signal definitions Table 24: Signal definitions SIGNAL Type SIGNAL Type RESET- DD07 3–state DD08 3–state DD06 3–state DD09 3–state DD05 3–state DD10 3–state DD04 3–state DD11 3–state DD03 3–state DD12 3–state...

  • Page 51: Signal Descriptions

    Table 25: Special signal definitions for Ultra DMA Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- 7.4 Signal descriptions DD00–DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Regis- ter and ECC access.
  • Page 52 DASP- This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5.0 volts through a 10 k. resistor. During a Power- On initialization or after RESET- is negated, DASP- shall be asserted by device 1 within 400 ms to indicate that device 1 is present.
  • Page 53 5V Power There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5 V Motor" input pin. These two input pins are tied together within the drive. DMACK- This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available.

  • Page 54: Interface Logic Signal Levels

    7.5 Interface logic signal levels The interface logic signals have the following electrical specifications: Input High Voltage (ViH) 2.0 V min./5.5 V max. Inputs Input Low Voltage (ViL) –0.5 V min./0.8 V max. Output High Voltage (VoH) 2.4 V min. Outputs Output Low Voltage (VoL) 0.5 V max.

  • Page 55: Pio Timings

    7.7 PIO timings The PIO cycle timings meet Mode 4 of the ATA-6 description. C S(1:0)- D A(2:0) D IO R -, D IO W - W rite data D D (15:0) R ead data D D (15:0) t7(*) t8(*) IO C S16-(*) IO R D Y (*) U p to ATA-2 (m ode-0,1,2)

  • Page 56: Multi Word Dma Timings

    7.8 Multi word DMA timings The Multi word DMA timings meet Mode 2 of the ATA-6 description. DMARQ tLR/tLW DMACK- tKR/tKW DIOR-/DIOW- READ DD(15:0) WRITE DD(15:0) Table 28: Multiword DMA cycle timings PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time –...

  • Page 57: Ultra Dma Timings

    7.9 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, 3, and 4 of the Ultra DMA Protocol. 7.9.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC DSTROBE tZAD DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxx RD Data...

  • Page 58: Host Pausing Read Dma

    7.9.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE Table 30: Ultra DMA cycle timings (Host Pausing Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)

  • Page 59: Host Terminating Read Dma

    7.9.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxx RD Data xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD Table 31: Ultra DMA cycle timings (Host Terminating Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4...

  • Page 60: Device Terminating Read Dma

    7.9.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD Table 32: Ultra DMA cycle timings (Device Terminating Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5...

  • Page 61: Initiating Write Dma

    7.9.5 Initiating Write DMA DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tCYC tCYC tACK HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD Table 33: Ultra DMA cycle timing (Initiating Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5...

  • Page 62: Device Pausing Write Dma

    7.9.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE Table 34: Ultra DMA cycle timing (Device Pausing Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)

  • Page 63: Device Terminating Write Dma

    7.9.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 35: Ultra DMA cycle timings (Device TerminatingWrite) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER...

  • Page 64: Host Terminating Write Dma

    7.9.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 36: Ultra DMA cycle timings (Host Terminating Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns)

  • Page 65: Drive Address Setting

    7.10 Drive address setting A jumper placed on the interface connector determines the drive address. Three drive addresses are shown below. Two addresses require the setting of a jumper. Figure 1 : Drive address setting Setting 1—Device 0 (Master) (no jumper is used) Setting 2—Device 1 (Slave) Setting 3—Cable Select Setting 4—Do not attach a jumper here...

  • Page 66: Addressing Of Hdd Registers

    7.11 Addressing of HDD registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA00–02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time.
  • Page 67 Part 2. Interface specification Travelstar 7K100 Hard Disk Drive Specification...
  • Page 68 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 69: General

    8.0 General 8.1 Introduction This specification describes the host interface of the Travelstar 7K100. The interface conforms to the Working Document of Information Technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-6) Revision 3b, dated 26 February 2001, with certain limitations described in Section 9.0, “Deviations from standard”...
  • Page 70 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 71: Deviations From Standard

    9.0 Deviations from standard The drive conforms to the referenced specifications, with the exception of the deviations described below. The interface conforms to the Working Document of Information Technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-6) Revision 3b, dated 26 February 2002, with the following deviation: Write Verify WRITE VERIFY command does not include read verification after write operation.
  • Page 72 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 73: Register

    10.0 Register Table 38: Register Set Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-) Data bus high impedence Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used Command block registers Data...

  • Page 74: Alternate Status Register

    10.1 Alternate Status Register Table 39: Alternate Status Register This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.

  • Page 75: Device Control Register

    10.4 Device Control Register Table 40: Device Control Register SRST -IEN Definitions HOB (high order byte) is defined by the 48-bit Address feature set. A write to any Command Register shall clear the HOB bit to zero. SRST (RST) Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the device.

  • Page 76: Device Register

    10.6 Device Register Table 42: Device Head/Register This register contains the device and head numbers. Definitions Binary encoded address mode select. When L = 0, addressing is by CHS mode. When L = 1, addressing is by LBA mode. Device. When DRV = 0, device 0 (Master) is selected. When DRV = 1, device 1 (Slave) is selected.

  • Page 77: Features Register

    10.8 Features Register This register is command specific. This register is used with the Set Features command, the S.M.A.R.T. Function Set command, and the Format Unit command. 10.9 LBA High Register This register contains Bits 16-23. At the end of the command this register is updated to reflect the current LBA Bits 16-23.

  • Page 78: Status Register

    10.13 Status Register Table 44: Status Register DRDY CORR This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read.

  • Page 79: General

    11.0 General 11.1 Reset response ATA has the following three types of resets: The device executes a series of electrical circuitry diagnostics, spins up the Power On Reset (POR) head disk assembly, tests speed and other mechanical parametric, and sets default values.

  • Page 80: Register Initialization

    11.2 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Table 46: Default Register Values Register Default Value Error Diagnostic Code Sector Count LBA Low LBA Mid LBA High Device...

  • Page 81: Diagnostic And Reset Considerations

    11.3 Diagnostic and Reset considerations The Set Max password, the Set Max security mode and the Set Max unlock counter are not retained over a Power On Reset but are retained over a Hard Reset or Soft Reset. For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On DASP–...

  • Page 82: Power-Off Considerations

    11.4 Power-off considerations 11.4.1 Load/Unload Load/Unload is a functional mechanism of the hard disk drive and is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the following commands. Table 49: Device behavior by ATA command Command Response Standby...

  • Page 83: Sector Addressing Mode

    You may then turn off the drive by doing the following steps: 1. Issue Standby Immediate or sleep command 2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in a typical case.) 3. Terminate power to drive This power-down sequence should be followed for entry into any system power-down state, system suspend state, or system hibernation state.

  • Page 84: Power Management Features

    11.6 Power management features The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.

  • Page 85: Standby Timer

    11.6.4 Standby timer The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the standby mode.

  • Page 86: Performance Idle Mode

    increase with increasing advanced power management levels. The advanced power management levels contain discrete bands, described in the section of Set Feature command in detail. This feature set uses the following functions: • A SET FEATURES subcommand to enable Advanced Power Management •...

  • Page 87: Function

    11.8 S.M.A.R.T. Function The intent of Self-monitoring, analysis, and reporting technology (S.M.A.R.T.) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.

  • Page 88: Operation With Power Management Modes

    11.8.6 S.M.A.R.T. operation with power management modes The device saves attribute values automatically on every head unload timing except the emergency unload, even if the attribute auto save feature is not enabled. The head unload is done not only by Standby, Standby Immediate, Sleep command, and Hard Reset, but also by the automatic power saving functions such as ABLE-3 or Standby timer.

  • Page 89: Password

    11.9.3 Password This function can have two types of passwords as described below. Master Password When the Master Password is set, the device does NOT enable the Device Lock Function, and the device CANNOT be locked with the Master Password, but the Master Password can be used for unlocking the locked device.
  • Page 90 11.9.4.3 Operation from POR after user password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media Access Command (*1) Command (*1) Erase Unit...
  • Page 91 11.9.4.4 User Password lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 92: Command Table

    11.9.5 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Table 51: Command table for device lock operation Device Mode Device Mode Command Command Locked Unlocked Frozen Locked Unlocked Frozen Check Power Mode...

  • Page 93: Protected Area Function

    11.10 Protected Area Function Protected Area Function provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the entire system main memory may also be dumped into the protected area to resume after a system power off. The LBA/CYL changed by the following commands affects the Identify Device Information.

  • Page 94: Set Max Security Extension Commands

    From this point the protected area cannot be accessed until the next Set Max ADDRESS command is issued. Any BIOS, device driver, or application software accesses the device as if it is a 528 MB device because the device behaves like a 528 MB device. 3.

  • Page 95: Address Offset Feature (Vendor Specific)

    The password, the Set Max security mode, and the unlock counter do not persist over a power cycle but they persist over a hardware or software reset. NOTE: If this command is immediately preceded by a Read Native MAX ADDRESS command, it shall be interpreted as a Set Max ADDRESS command regardless of Feature register value.

  • Page 96: Identify Device Data

    Figure 6: Device address map before and after Set Feature 11.11.2 Identify Device Data Identify Device data, word 83, bit 7 indicates the device supports the Address Offset Feature. Identify Device data, word 86, bit 7 indicates the device is in Address Offset mode. 11.11.3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error, even if the access protection is removed by a Set Max Address command.

  • Page 97: Seek Overlap

    11.12 Seek Overlap The drive provides accurate seek time measurement method. The seek command is usually used to measure the device seek time by accumulating execution time for a number of seek commands. With typical implementation of the seek command, this measurement must include the device and host command overhead. To eliminate this overhead, the drive overlaps the seek command as described below.

  • Page 98: Reassign Function

    11.14 Reassign Function The Reassign Function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. The one entry can register 256 consecutive sectors maximum. This reassignment information is registered internally, and the information is available right after completing the reassign function.

  • Page 99: 48-Bit Address Feature Set

    11.15 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. The following commands unique to the 48-bit Address feature set: •...
  • Page 100 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 101: Command Protocol

    12.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.

  • Page 102: Data Out Commands

    f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets BSY = 0 and DRQ=1 and interrupts the host.

  • Page 103: Non-Data Commands

    • Write Sector(s) • Write Sector(s) EXT • Write Verify Execution includes the transfer of one or more 512 byte (> 512 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, LBA, and Device Registers. 2.
  • Page 104 • Flush Cache EXT • Format Unit • Idle • Idle Immediate • Initialize Device Parameters • Read Native Max ADDRESS • Read Native Max ADDRESS EXT • Read Verify Sector(s) • Read Verify Sector(s) EXT • Recalibrate • Security Erase Prepare •...

  • Page 105: Dma Data Transfer Commands

    12.4 DMA Data Transfer commands: The following are DMA Data Transfer commands: • Read DMA • Read DMA EXT • Write DMA • Write DMA EXT Data transfers using DMA commands differ in two ways from PIO transfers: • Data transfers are performed using the Slave DMA channel •...
  • Page 106 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 107: Command Descriptions

    13.0 Command descriptions The table below shows the commands that are supported by the device. Table 55: “Command Set (subcommand)” on page 96 shows the subcommands that are supported by each command or feature. Table 53: Command Set (1 of 2) Code Binary Code Bit Protocol...

  • Page 108: Table 54. Command Set (2 Of 2)

    Table 54: Command Set (2 of 2) Binary Code Bit Protocol Command Code (Hex) 7 6 5 4 3 2 1 0 Sense Condition 1 1 1 1 0 0 0 0 Set Features 1 1 1 0 1 1 1 1 Set Max ADDRESS 1 1 1 1 1 0 0 1 Set Max ADDRESS EXT...
  • Page 109 Protocol: 1 : PIO data IN command 3 : Non data command + : Vendor specific command 2 : PIO data OUT command 4 : DMA command Travelstar 7K100 Hard Disk Drive Specification...

  • Page 110: Table 55. Command Set (Subcommand)

    Table 55: Command Set (subcommand) Command Feature Command (Subcommand) Code (Hex) Register (Hex) S.M.A.R.T. Function S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T. Save Attribute Values S.M.A.R.T. Execute Off-line Immediate S.M.A.R.T. Read Log Sector S.M.A.R.T. Write Log Sector S.M.A.R.T.
  • Page 111 ture. The following symbols are used in the command descriptions. Input registers This indicates that the bit is always set to 0. This indicates that the bit is always set to 1. Head number. This indicates that the head number part of the Device/Head Register is an input parameter and will be set by the device.

  • Page 112: Check Power Mode (E5H/98H)

    13.1 Check Power Mode (E5h/98h) Table 56: Check Power Mode Command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 113: Device Configuration Overlay (B1H)

    13.2 Device Configuration Overlay (B1h) Table 57: Device Configuration Overlay Command (B1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 114: Device Configuration Identify (Subcommand C2H).99

    13.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.

  • Page 115: Table 59. Device Configuration Overlay Data Structure

    Table 59: Device Configuration Overlay Data structure Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved...

  • Page 116: Execute Device Diagnostic (90H)

    13.3 Execute Device Diagnostic (90h) Table 61: Execute Device Diagnostic command (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 117: Flush Cache (E7H)

    13.4 Flush Cache (E7h) Table 62: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 118: Flush Cache Ext (Eah)

    13.5 Flush Cache EXT (EAh) Table 63: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 119: Format Track (50H: Vendor Specific)

    13.6 Format Track (50h: vendor specific) Table 64: Format Track command (50h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 120: Format Unit (F7H: Vendor Specific)

    13.7 Format Unit (F7h: vendor specific) Table 65: Format Unit command (F7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 121: Identify Device (Ech)

    13.8 Identify Device (ECh) Table 66: Identify Device command (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 122: Table 67. Identify Device Information. (Part 1 Of 7)

    Table 67: Identify device information. (Part 1 of 7) Word Content Description 045AH drive classi- bit assignments fication 15(=0) 1=ATAPI device, 0=ATA device 14(=0) 1=format speed tolerance gap required 13(=0) 1=track offset option available 12(=0) 1=data strobe offset option available 11(=0) 1=rotational speed tolerance >...

  • Page 123: Table 68. Identify Device Information. (Part 2 Of 7)

    Table 68: Identify device information. (Part 2 of 7) Word Content Description 0000H * Capable of double word I/O, '0000'= cannot perform 0F00H Capabilities, bit assignments: 15-14(=0) Reserved 13(=0) Standby timer value are vendor specific 12(=0) Reserved 11(=1) IORDY Supported 10(=1) IORDY can be disabled 9(=1)

  • Page 124: Table 69. Identify Device Information. (Part 3 Of 7)

    Table 69: Identify device information. (Part 3 of 7) Word Content Description 0003H Flow Control PIO Transfer Modes Supported 15- 8(=0) Reserved 7- 0(=3) Advanced PIO Transfer Modes Supported '11' = PIO Mode 3 and 4 Supported 0078H Minimum Multiword DMA Transfer Cycle Time Per Word 15- 0(=78h) Cycle time in nanoseconds (120 ns, 16.6 MB/s) 0078H Manufacturer's Recommended Multiword DMA Transfer Cycle Time...

  • Page 125: Table 70. Identify Device Information. (Part 4 Of 7)

    Table 70: Identify device information. (Part 4 of 7) Word Content Description 7FE8H Command set supported 15(=0) Always 14(=1) Always 13(=1) 1=FLUSH CACEH EXT command supported 12(=1) 1=FLUSH CACHE command supported 11(=1) 1=Device Configuration Overlay command supported 10(=1) 1=48-bit Address feature set supported 9(=1) 1=Automatic Acoustic Management supported ** 8(=1)

  • Page 126: Table 71. Identify Device Information

    Table 71: Identify device information. (Part 5 of 7 Word Content Description 3XXXH Command set/feature enabled 15-14(=0) Reserved 13(=1) 1=FLUSH CACHE EXT command supported 12(=1) 1=FLUSH CACHE command supported 11(=x) 1=Device Configuration Overlay supported 10(=1) 1=48-bit Address feature set supported 9(=X) 1=Automatic Acoustic Management enabled 8(=X)

  • Page 127: Table 72. Identify Device Information. (Part 6 Of 7)

    Table 72: Identify device information. (Part 6 of 7) Word Content Description 40XXH Current Advanced Power Management level 15- 8(=40h) Reserved 7- 0(=xxh) Current Advanced Power Management level set by Set Features Command (01h to FEh) XXXXH Current Master Password Revision Codes XXXXH Hardware reset results 15-13...

  • Page 128: Table 73. Identify Device Information. (Part 7 Of 7)

    Table 73: Identify device information. (Part 7 of 7) Word Content Description 0XXXH Security Mode Feature. Bit assignments 15-9(=0) Reserved 8(=X) Security Level: 1= Maximum, 0= High 7-6(=0) Reserved 5(=0) 1=Enhanced security erase supported 4(=0) 1=Security count expired 3(=0) 1=Security Frozen 2(=0) 1=Security Locked 1(=0)

  • Page 129: Table 74. Number Of Cylinders/Heads/Sectors

    Table 74: Number of cylinders/heads/sectors Microcode revision MCxOAxxx HTS721010G9AT00 Number of cylinders 3FFFh Number of heads Buffer size 3AE6h Total number of user BA52230h addressable sectors Microcode revision MCxOAxxx HTS721080G9AT00 Number of cylinders 3FFFh Number of heads Buffer size 3AE6h Total number of user 950F8B0h addressable sectors...

  • Page 130: Idle (E3H/97H)

    13.9 Idle (E3h/97h) Table 75: Idle command (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 131: Idle Immediate (E1H/95H)

    13.10 Idle Immediate (E1h/95h) Table 76: Idle Immediate command (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 132: Initialize Device Parameters (91H)

    13.11 Initialize Device Parameters (91h) Table 77: Initialize Device Parameters command (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 133: Read Buffer (E4H)

    13.12 Read Buffer (E4h) Table 78: Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 134: Read Dma (C8H/C9H)

    13.13 Read DMA (C8h/C9h) Table 79: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 135 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. LBA Low This indicates the sector number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 0–7.

  • Page 136: Read Dma Ext (25H)

    13.14 Read DMA EXT (25h) Table 80: Read DMA EXT (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 137 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)

  • Page 138: Read Log Ext (2Fh)

    13.15 Read Log Ext (2Fh) Table 81: Read Log Ext Command (2Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...

  • Page 139: General Purpose Log Directory

    Table 82: Log Address Definition Log Address Content Feature set Type Log directory Read Only Extended Comprehensive SMART error log SMART error logging Ready Only SMART self-test log SMART self-test See Note Extended SMART self-test log SMART self-test Read Only Streaming Performance log Streaming Read Only...

  • Page 140: Extended Comprehensive Smart Error Log

    The value of the General Purpose Logging Version word shall be 0001h. A value of 0000h indicates that there is no General Purpose Log Directory. The logs at log addresses 80-9Fh shall each be defined as 16 sectors long. 13.15.2 Extended Comprehensive SMART Error Log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log.

  • Page 141: Table 86. Command Data Structure

    Description Bytes Offset 3rd error log data structure 4th error log data structure 5th error log data structure Error data structure 13.15.2.3.2 Data format of command data structure Table 86: Command data structure Description Bytes Offset Device Control register Features register (7:0) (see Note) Features register (15:8) Sector count register(7:0) Sector count register(15:8)

  • Page 142: Extended Self-Test Log Sector

    13.15.2.3.3 Data format of error data structure Table 87: Error data structure Description Bytes Offset Reserved Error register (7:0) Sector count register(7:0)(See Note) Sector count register(15:8)(See Note) Sector number register(7:0) Sector number register(15:8) Cylinder Low register (7:0) Cylinder Low register (15:8) Cylinder High register (7:0) Cylinder High register (15:8) Device/Head register...
  • Page 143 The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log, defined in 11.42.6, "Self-test log data structure" on page0203, shall also be included in the Extended SMART self-test log with all 48-bit entries. Description Bytes Offset...

  • Page 144: Read Long (22H/23H)

    13.16 Read Long (22h/23h) Table 88: Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 145 LBA Low This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7. (L = 1) LBA High/Low This indicates the cylinder number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Low), 16–23 (High).

  • Page 146: Read Multiple (C4H)

    13.17 Read Multiple (C4h) Table 89: Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 147 LBA High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Mid), 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 24–27.

  • Page 148: Read Multiple Ext (29H)

    13.18 Read Multiple EXT (29h) Table 90: Read Multiple EXT (29h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 149: Read Native Max Address (F8H)

    13.19 Read Native Max ADDRESS (F8h) Table 91: Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...

  • Page 150: Read Native Max Address Ext (27H)

    13.20 Read Native Max ADDRESS EXT (27h) Table 92: Read Native Max ADDRESS EXT (27h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...

  • Page 151: Read Sectors (20H/21H)

    13.21 Read Sectors (20h/21h) Table 93: Read Sectors (20h/21h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 152: Read Sector(S) Ext (24H)

    13.22 Read Sector(s) EXT (24h) Table 94: Read Sector(s) EXT Command (24h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 153 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)

  • Page 154: Read Verify Sectors (40H/41H)

    13.23 Read Verify Sectors (40h/41h) Table 95: Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 155 LBA High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 156: Ready Verify Sector(S) Ext (42H)

    13.24 Ready Verify Sector(s) EXT (42h) Table 96: Read Verify Sector(s) EXT Command (42h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
  • Page 157 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)

  • Page 158: Recalibrate (1Xh)

    13.25 Recalibrate (1xh) Table 97: Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 159: Security Disable Password (F6H)

    13.26 Security Disable Password (F6h) Table 98: Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 160: Security Erase Prepare (F3H)

    13.27 Security Erase Prepare (F3h) Table 100: Security Erase Prepare (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 161: Security Erase Unit (F4H)

    13.28 Security Erase Unit (F4h) Table 101: Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 162 This command disables the security mode feature (device lock function), however, the master password is still stored internally within the device and may be reactivated later when a new user password is set. If you execute this command on disabling the security mode feature (device lock function), the password sent by the host is NOT compared with the Master Password and the User Password.

  • Page 163: Security Freeze Lock (F5H)

    13.29 Security Freeze Lock (F5h) Table 103: Security Freeze Lock (F5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 164: Security Set Password (F1H)

    13.30 Security Set Password (F1h) Table 104: Security Set Password (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 165 Security Level A zero indicates a High level, a one indicates a Maximum level. If the host sets the High level and the password is forgotten then the Master Password can be used to unlock the device. If the host sets the Maximum level and the user password is forgotten, only a Security Erase Prepare/Security Unit command can unlock the device and all data will be lost.

  • Page 166: Security Unlock (F2H)

    13.31 Security Unlock (F2h) Table 106: Security Unlock (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 167: Seek (7Xh)

    13.32 Seek (7xh) Table 107: Seek (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 168: Sense Condition (F0H: Vendor Specific)

    13.33 Sense Condition (F0h: vendor specific) Table 108: Sense Condition (F0h: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...

  • Page 169: Set Features (Efh)

    13.34 Set Features (EFh) Table 109: Set Features (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 170 Disable Power-Up in Standby feature set Disable Address Offset mode Enable read look-ahead feature 4 bytes of ECC apply on Read Long/Write Long commands Disable Automatic Acoustic Management feature set Enable reverting to power on defaults Note 1. When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer mechanism.

  • Page 171: Set Max Address (F9H)

    13.35 Set Max ADDRESS (F9h) Table 110: Set Max ADDRESS (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 172 If a host protected area has been established by a Set Max Address Ext command, the device shall return command aborted Output parameters to the device Feature Destination code for this command SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK When the Set Max ADDRESS command is executed, this register is ignored.

  • Page 173: Set Max Address Ext (37H)

    13.36 Set Max ADDRESS EXT (37h) Table 111: Set Max ADDRESS EXT Command (37h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
  • Page 174 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by Set Max Address Ext command is preserved by POR. When B=0, MAX Address which is set by Set Max Address Ext command will be lost by POR.

  • Page 175: Set Multiple (C6H)

    13.37 Set Multiple (C6h) Table 112: Set Multiple command (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 176: Sleep (E6H/99H)

    13.38 Sleep (E6h/99h) Table 113: Sleep (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 177: Function Set (B0H)

    13.39 S.M.A.R.T. Function Set (B0h) Table 114: S.M.A.R.T. Function Set (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 178: Function Subcommands

    13.39.1 S.M.A.R.T. Function Subcommands 13.39.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the S.M.A.R.T. Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register.

  • Page 179: Device Attribute Data Structure

    13.39.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h) This subcommand causes the device to immediately initiate the set of activities that collect Attribute data in an off- line mode (off-line routine) or execute a self-test routine in either captive or off-line mode. The LBA Low register shall be set to specify the operation to be executed.
  • Page 180 After the scan of the selected spans described above, a user may wish to have the rest of media read scanned as an off-line scan. In this case, the user shall set the flag to enable off-line scan in addition to the other settings. If an error occurs during the scanning of the test spans, the error is reported in the self-test execution status in the SMART READ DATA response and the off-line scan is not executed.
  • Page 181 13.39.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h) This command returns the specified log sector contents to the host. The 512 bytes of data are returned at a command and the Sector Count value shall be set to one. The LBA Low shall be set to specify the log sector address.
  • Page 182 13.39.1.11 S.M.A.R.T. Return Status (subcommand DAh) This subcommand is used to communicate the reliability status of the device to the host's request. Upon receipt of the S.M.A.R.T. Return Status subcommand the device asserts BSY, saves any updated Attribute Values to the reserved sector, and compares the updated Attribute Values to the Attribute Thresholds.

  • Page 183: Device Attribute Data Structure

    13.39.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte ordering, namely, that the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 184: Individual Attribute Data Structure

    13.39.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Byte Offset Value Attribute ID Number (01h to FFh) binary Status Flags bit flags Bit 0 Pre-Failure/Advisory Bit 1...

  • Page 185: Table 116. Status Flag Definitions

    Table 116: Status Flag definitions Flag Name Definition Pre-Failure/ If bit = 0, an Attribute Value less than or equal to its Advisory bit corresponding Attribute Threshold indicates an Advisory condition where the usage or age of the device has exceeded its intended design life period.

  • Page 186: Self-Test Execution Status

    13.39.2.4 Self-test execution status Definition Percent Self-test remaining. An approximation of the percent of the self-test routine remaining until completion given in ten percent increments. Valid values are 0 through 9. Current Self-test execution status. 0 The self-test routine completed without error or has never been run. 1 The self-test routine was aborted by the host.

  • Page 187: Capability

    Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit Self-test routing is not implemented Self-test routine is implemented Reserved (0) Selective self-test routine is not implemented Selective self-test routine is not implemented Selective self-test routine is implemented Reserved (0) 13.39.2.8 S.M.A.R.T.

  • Page 188: Device Attribute Thresholds Data Structure

    13.39.3 Device Attribute Thresholds data structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All multibyte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte ordering, that is, that the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 189: Data Structure Checksum

    13.39.3.3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures. 13.39.3.4 Attribute Threshold These values are preset at the factory and are not meant to be changeable. However, the host might use the "S.M.A.R.T.

  • Page 190: Log Directory

    13.39.4 S.M.A.R.T. Log Directory Table 118 defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Directory is on S.M.A.R.T. Log Address zero and is defined as one sector long. Table 119: S.M.A.R.T. Log Directory Description Bytes Offset S.M.A.R.T.

  • Page 191: Table 122. Command Data Structure

    13.39.5.4 Error log data structure The data format of each error log structure is shown below. Table 121: Command data structure Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure 13.39.5.5 Command data structure...

  • Page 192: Table 123. Error Data Structure

    13.39.5.6 Error data structure Data format of error data structure is shown below. Table 123: Error data structure Description Byte Offset Reserved Error register Sector count register LBA Low register LBA Mid register LBA High register Device register Status register Extended error data (vendor spe- cific) State...

  • Page 193: Self-Test Log Data Structure

    13.39.6 Self-test log data structure The following defines the 512 bytes that make up the Self-test log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI-6 specifications for byte ordering. Table 124: Self-test log data structure Description Byte Offset Data structure revision...

  • Page 194: Error Reporting

    Ending LBA for test span 5 Reserved Reserved Vendor specific 152h Vendor specific Current LBA under test 1ECh Read Current span under test 1F4h Read Feature flags Vendor Specific 1F8h Vendor specific Selective self test pending time 2 1FCh Reserved 1FEh Reserved Data structure checksum...

  • Page 195: Standby (E2H/96H)

    13.40 Standby (E2h/96h) Table 126: Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 196: Standby Immediate (E0H/94H)

    13.41 Standby Immediate (E0h/94h) Table 127: Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 197: Write Buffer (E8H)

    13.42 Write Buffer (E8h) Table 128: Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 198: Write Dma (Cah/Cbh)

    13.43 Write DMA (CAh/CBh) Table 129: Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 199 LBA Low This indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7. (L = 1) LBA High/Mid This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High).

  • Page 200: Write Dma Ext (35H)

    13.44 Write DMA EXT (35h) Table 130: Write DMA (35h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 201 LBA High Current LBA (23-16) LBA High Previous LBA (47-40) Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1)

  • Page 202: Write Log Ext (3Fh)

    13.45 Write Log Ext (3Fh) Table 131: Write Log Ext (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 203: Write Long (32H/33H)

    13.46 Write Long (32h/33h) Table 132: Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 204 LBA High/Mid This indicates the cylinder number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 24–27.

  • Page 205: Write Multiple (C5H)

    13.47 Write Multiple (C5h) Table 133: Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 206: Write Multiple Ext (39H)

    13.48 Write Multiple EXT (39h) Table 134: Write Multiple EXT (39h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 207 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)

  • Page 208: Write Sectors (30H/31H)

    13.49 Write Sectors (30h/31h) Table 135: Write Sectors Command (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 209 LBA High/Mid This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 210: Write Sectors(S) Ext (34H)

    13.50 Write Sectors(s) EXT (34h) Table 136: Write Sector(s) EXT Command (34h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...

  • Page 211: Write Verify (3Ch: Vendor Specific)

    Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
  • Page 212 Travelstar 7K100 Hard Disk Drive Specification...

  • Page 213: Time-Out Values

    14.0 Time-out values The timing of BSY and DRQ in Status Register are shown in the table below. Table 137: Time-out values INTERVAL START STOP TIME-OUT Power On Device Busy After Power On Status Register BSY=1 400 ns Power On Device Ready After Power On Status Register BSY=0...
  • Page 214 Note 1. For SECURITY ERASE UNIT command, the execution time is referred to 13.28, “Security Erase Unit (F4h)” on page 146. Note 2. For FORMAT UNIT command, the execution time is referred to 13.7, “Format Unit (F7h: vendor specific)” on page 105. Note 3.

  • Page 215: Appendix

    15.0 Appendix 15.1 Commands Support Coverage The table below compares the command support coverage of the Travelstar 7K100 with the ATA-6 defined com- mand set. The third column indicates the capability of the drive for those commands. Implementation for ATA-6 Category Code Command Name Travelstar 7K100...
  • Page 216 Implementation for ATA-6 Category Code Command Name Travelstar 7K100 Type READ DMA Mandatory READ DMA Obsoleted WRITE DMA Mandatory WRITE DMA Obsoleted WRITE DMA QUEUED Optional CFA WRITE MULTIPLE W/O ERASE Optional (Note 7) GET MEDIA STATUS Optional (Note 7) MEDIA LOCK Optional (Note 7) MEDIA UNLOCK...

  • Page 217: Set Features Commands Support Coverage

    Note 5. S.M.A.R.T. Function Set Note 6. Security Mode Feature Set Note 7. Removable 15.2 SET FEATURES Commands Support Coverage The following table provides a list of Feature Registers, Feature Names, and implementation for the Travelstar 7K100. The third column indicates whether or not the Travelstar 7K100 has the capability of executing the command in comparison to the ATA-6 defined command set.

  • Page 218: Changes From The Travelstar 5K100

    15.3 Changes from the Travelstar 5K100 The changes between the Travelstar 7K100 and the Travelstar 5K100 are listed below: • Product ID • Time to format Travelstar 7K100 Hard Disk Drive Specification...
  • Page 219 Index Acoustics .........................32 Address Feature Set ......................85 Address Offset Feature ....................81 Advanced Power Management (ABLE-3) feature ............71 Appendix .........................199 BSMI mark ........................33 Cable noise interference ....................25 Capacity, formatted ......................11 CE mark ..........................33 Check Power Mode ......................97 Command descriptions ....................93 Command overhead ......................13 Command protocol ......................87 Command table .......................78 Commands Support Coverage ..................199...
  • Page 220 Discrete tone penalty ......................32 Drive Address Register ....................61 Drive address setting .......................51 Drive characteristics .......................11 Drive handling precautions .....................3 Drive ready time ......................15 Electrical interface specification ..................35 Electromagnetic compatibility ..................33 Emergency unload ......................26 Environment ........................21 Execute Device Diagnostic .....................101 Failure prediction (S.M.A.R.T.) ..................25 Features Register ......................63 Fixed-disk subsystem ......................9 Fixed-disk subsystem description ...................9...
  • Page 221 Load/unload ........................26 Magnetic fields .......................23 Mechanical positioning ....................14 Mechanical specifications ....................28 Mode transition time .......................16 Mounting hole locations ....................28 Mounting orientation ......................29 Non-data commands .......................89 Operating modes description ........................16 Packaging ........................34 Performance characteristics ....................13 Physical cylinders ......................12 PIO timings ........................41 Power consumption effiency ..................24 Power management commands ..................70 Power management features ...................70...
  • Page 222 Register ...........................59 Register initialization ......................66 Register set ........................59 Reset response .........................65 Reset timings ........................40 S.M.A.R.T. Function ......................73 S.M.A.R.T. Function Set ....................162 Safety ..........................34 Secondary circuit protection ...................34 Sector Addressing Mode ....................69 Sector Count Register .....................63 Sectors/Track ........................12 Security Disable Password ....................144 Security Erase Unit ......................146 Security Set Password .....................149 Security Unlock ......................151...
  • Page 223 Transition time ........................72 UL approval ........................34 Vibration .........................30 Write Buffer ........................182 Write Cache function ......................83 Zone ..........................12...
  • Page 225 References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information pur- poses only and does not constitute a warranty.

This manual is also suitable for:

Hts721010g9at00Hts721080g9at00Hts721060g9at00

Table of Contents