Power Save Configuration Registers; Miscellaneous Registers; Table 8-10: Suspend Refresh Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

Page 102

8.2.6 Power Save Configuration Registers

Power Save Configuration Register
REG[1Ah]
n/a n/a
bit 3
bits 2-1
Suspend Refresh Select Bits [1:0]
bit 0

8.2.7 Miscellaneous Registers

Miscellaneous Disable Register
REG[1Bh]
Host Interface
n/a
Disable
bit 7
S1D13504
X19A-A-002-18
n/a n/a
LCD Power Disable
When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR "On/Off"
state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output
is controlled by the panel on/off sequencing logic. See Table 5-8: "Summary of Power On / Reset
Options," on page 31.
Suspend Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh to use in Suspend mode.

Table 8-10: Suspend Refresh Selection

00
01
1x
Note
These bits should not be changed when suspend mode is enabled.
Software Suspend Mode Enable
When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled.
n/a n/a
Host Interface Disable
This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When
this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through
REG[2Fh], and REG[1Bh] are inaccessible.
Suspend
LCD Power
Refresh
Disable
Select Bit 1
DRAM Refresh Type
CBR Refresh
Self-Refresh
No Refresh
n/a n/a
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Suspend Software
Refresh Suspend
Select Bit 0 Mode Enable
Half Frame
n/a
Buffer Disable
Hardware Functional Specification
Issue Date: 01/01/30
RW
RW