Fujitsu MB15F74UV Datasheet page 10

Dual serial input pll frequency synthesizer
Table of Contents

Advertisement

MB15F74UV
Prescaler Data Setting
Divide ratio
Prescaler divide ratio IF-PLL
Prescaler divide ratio RF-PLL
• Charge Pump Current Setting
Current value
6.0 mA
1.5 mA
LD
fout output Selectable Bit Setting
/
LD/fout pin state
LD output
fr
IF
fr
fout
RF
output
fp
fp
RF
Phase Comparator Phase Switching Data Setting
Phase comparator input
fr
fp
fr
fp
fr
fp
Z
High-impedance
:
Depending upon the VCO and LPF polarity, FC bit should be set.
(1) VCO polarity FC
(2) VCO polarity FC
Note : Give attention to the polarity for using active type LPF.
10
SW
"1"
32/33
64/65
CS
1
0
LDS
0
0
0
1
1
1
IF
1
FC
,
"1"
IF
RF
Do
, Do
IF
RF
H
L
Z
"1"
"0"
SW
"0"
64/65
128/129
T1
T2
0
0
1
0
1
1
0
0
1
0
0
1
1
1
FC
,
"0"
IF
RF
Do
, Do
IF
RF
L
H
Z
High
VCO Output
Frequency
LPF Output voltage
(1)
(2)
Max

Advertisement

Table of Contents
loading

Table of Contents