Fujitsu MB15C02 Datasheet page 13

(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains
the divide ratio setting data and into the control register which contains the control bit. The logical product (through
the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the
latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is enabled and the
divide ratio data from the shift register is loaded into the selected counter (s).
AND
Data
C*
Clock
LE
AND
Prescaler
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table 2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table2.2
represent the divide ratio of programmable counter.
Table.2.1 Swallow counter divider A
Divide
A A A
ratio
0 1 2
(A)
0 0 0 0
1 1 0 0
⋅ ⋅ ⋅ ⋅
63 1 1 1
14-bit binary programmable reference counter
6
6-bit binary swallow counter 12-bit binary programmable
Figure 4. The flow of serial data
Table. 2 Divide ratio for the programmable divider
Table2.2 Programmable counter divider N
Divide
A A A
ratio
3 4 5
(N)
0 0 0 5
0 0 0 6
⋅ ⋅ ⋅
1 1 1 4095
14
14-bit latch
14
18-bit shift register
18
18-bit latch
12
counter
N N N N N
0 1 2 3 4
1 0 1 0 0
0 1 1 0 0
⋅ ⋅ ⋅ ⋅ ⋅ ⋅
1 1 1 1 1
MB15C02
Programmable
reference divider
Programmable
divider
* : Control register
N N N N N N
5 6 7 8 9 10
0 0 0 0 0 0
0 0 0 0 0 0
⋅ ⋅ ⋅ ⋅ ⋅ ⋅
1 1 1 1 1 1
Note: Less than 5 is prohibited.
N
11
0
0
⋅
1
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