Motorola DSP56012 User Manual page 78

Memory, Operating Modes, and Interrupts
Interrupt Priority Register
Address
P: $0018
P: $001A
P: $001C
P: $001E
P: $0020
P: $0022
P: $0024
P: $0026
P: $0028
P: $002A
P: $002C
P: $002E
P: $0030
P: $0032
P: $0034
P: $0036
.
.
.
P: $003C
P: $003E
P: $0040
P: $0042
P: $0044
P: $0046
P: $0048
P: $004A
P: $004C
P: $004E
P: $0050
3-18
Table 3-5 Interrupt Vectors (Continued)
SAI Right Channel Receiver if RXIL = 0
SAI Receiver Exception if RXIL = 0
Reserved
NMI
SHI Transmit Data
SHI Transmit Underrun Error
SHI Receive FIFO Not Empty
Reserved
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
Reserved
Host Receive Data
Host Transmit Data
Host Command (Default)
Reserved
.
.
.
Reserved
Illegal Instruction
SAI Left Channel Transmitter if TXIL = 1
SAI Right Channel Transmitter if TXIL = 1
SAI Transmitter Exception if TXIL = 1
SAI Left Channel Receiver if RXIL = 1
SAI Right Channel Receiver if RXIL = 1
SAI Receiver Exception if RXIL = 1
Reserved
Reserved
DAX Transmit Underrun Error
DSP56012 User's Manual
Interrupt Source
MOTOROLA