NXP Semiconductors UM10204 User Manual

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UM10204

C-bus specification and user manual

Rev. 5 — 9 October 2012

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Keywords

I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,

Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL

Abstract

Philips Semiconductors (now NXP Semiconductors) developed a simple

bidirectional 2-wire bus for efficient inter-IC control. This bus is called the

Inter-IC or I

(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional

data transfers can be made at up to 100 kbit/s in the Standard-mode, up to

400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or

up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a

uni-directional mode with data transfers of up to 5 Mbit/s.

C-bus. Only two bus lines are required: a serial data line

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Page 1 I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+, Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I C-bus.
Page 2 For sales office addresses, please send an email to: salesaddresses@nxp.com UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 2 of 64...
Page 3: Introduction
To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I C-bus.
Page 4: Designer Benefits
No need to design bus interfaces because the I C-bus interface is already integrated on-chip. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 4 of 64...
Page 5: Manufacturer Benefits
IC from the bus and clipping on its successor. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 5 of 64...
Page 6: Ic Designer Benefits
C-bus (see Figure UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 6 of 64...
Page 7 I C-bus specification and which system configurations use them. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 7 of 64...
Page 8: Sda And Scl Signals
Fig 3. Devices with various supply voltages sharing the same bus UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 8 of 64...
Page 9: Sda And Scl Logic Levels
START and repeated START conditions, unless Sr is particularly relevant. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 9 of 64...
Page 10: Byte Format
5. A master-receiver must signal the end of the transfer to the slave transmitter. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 12 Master 1 sends a repeated START condition and master 2 sends a STOP condition. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 13: Clock Stretching
Fig 10. The first byte after the START procedure UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 13 of 64...
Page 14 Refer to individual component data sheets. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 14 of 64...
Page 15: 10-Bit Addressing
1111 1XX are reserved for future I C-bus enhancements. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 15 of 64...
Page 16 DATA byte contains the eight least-significant bits of the master address. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 16 of 64...
Page 17: Reserved Addresses
(see Figure 16). UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 17 of 64...
Page 19: Software Reset
An acknowledge clock pulse (ACK) • A repeated START condition (Sr). UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 19 of 64...
Page 20: Bus Clear
Figure 20) is an optional 3-byte read-only (24 bits) word giving the following information: • Twelve bits with the manufacturer name, unique per manufacturer (for example, NXP) • Nine bits with the part identification, assigned by manufacturer (for example, PCA9698) •...
Page 21 Device ID sequence until a NACK has been detected. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 22 Atmel Designers of new I C devices who want to implement the device ID feature should contact NXP at i2c.support@nxp.com to have a unique manufacturer ID assigned. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Page 23: Ultra Fast-Mode I C-Bus Protocol
1 002aag654 Fig 21. Example of UFm I C-bus configuration UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 23 of 64...
Page 24 10-bit slave address General Call address Software Reset START byte Device ID UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 24 of 64...
Page 25: Usda And Uscl Signals
HIGH transition on the USDA line while USCL is HIGH defines a STOP condition. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 26: Byte Format
002aag657 Fig 25. Data transfer on the UFm I C-bus UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 26 of 64...
Page 27: Acknowledge (Ack) And Not Acknowledge (Nack)
‘1’ on the ninth bit for the slave to conform to the I C-bus protocol. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 27 of 64...
Page 28: 10-Bit Addressing
1111 1XX are reserved for future I C-bus enhancements. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 28 of 64...
Page 29: Reserved Addresses In Ufm
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 29 of 64...
Page 30: General Call Address
There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 30 of 64...
Page 31: Unresponsive Slave Reset
3.2.14 Device ID The Device ID field is not supported in UFm. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 31 of 64...
Page 32: Other Uses Of The I C-Bus Communications Protocol
10 kHz is not SMBus compliant since the SMBus devices may time-out. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 33: Time-Out Feature
Smart Batteries), and will inter-operate as long as they adhere to the SMBus electrical specifications for their class. NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The main difference is the current sink capability with V = 0.4 V.
Page 34: Pmbus - Power Management Bus
For more information, refer to: www.nxp.com/redirect/intel.com/design/servers/ipmi. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 34 of 64...
Page 35: Advanced Telecom Computing Architecture (Atca)
– Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 35 of 64...
Page 38: Serial Data Format In Hs-Mode
Hs-mode master device is software programmable and is chosen by the System Designer. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 38 of 64...
Page 39 Sr SLAVE ADD. msc616 Fig 33. Data transfer format in Hs-mode UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 39 of 64...
Page 40: Switching From F/S-Mode To Hs-Mode And Back
5. Enables the current source pull-up circuit of its SCLH output stage at time t UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 41: Hs-Mode Devices At Lower Speed Modes
F/S-mode bus system, allowing the SDA and SCL pins (if present) on the Hs-mode master device to be used for other functions. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 41 of 64...
Page 42: Mixed Speed Modes On One Serial Bus System
Section 3.1.7. During Hs-mode transfer, however, the bridge UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 42 of 64...
Page 44: Standard, Fast-Mode And Fast-Mode Plus Transfer In A Mixed-Speed Bus System
Fast-mode specification (see t Table 10). UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 44 of 64...
Page 45: Timing Requirements For The Bridge In A Mixed-Speed Bus System
Fast-mode specification for the SDA and SCL lines. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 46: Ultra Fast-Mode
In the latter case, the bit transfer rate is reduced. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 46 of 64...
Page 47 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 9. Characteristics of the SDA and SCL I/O stages n/a = not applicable. Symbol Parameter Conditions...
Page 48 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 10. Characteristics of the SDA and SCL bus lines for Standard, Fast, and Fast-mode Plus I C-bus devices Symbol Parameter...
Page 49 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t 250 ns must then be met.
Page 50: Hs-Mode Devices
12, allowing a maximum bit rate of 1.7 Mbit/s. For UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 50 of 64...
Page 51 Special purpose devices such as multiplexers and switches may exceed this capacitance because they connect multiple paths together. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 52 An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 53: Ultra Fast-Mode Devices
Input filters on the USDA and USCL slave inputs suppress noise spikes of less than 10 ns. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 54 Fig 40. Definition of timing for Ultra Fast-mode devices on the I C-bus UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 54 of 64...
Page 55: Electrical Connections Of I C-Bus Devices To The Bus Lines
42. The traces are calculated using p(min) Equation – OL max -------------------------------------- p min UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 55 of 64...
Page 56: Operating Above The Maximum Allowable Bus Capacitance
UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012...
Page 57: Switched Pull-Up Circuit
Refer to application notes AN255, I C / SMBus Repeaters, Hubs and Expanders and AN262, PCA954x Family of I C / SMBus Multiplexers and Switches for more details on this subject and the devices available from NXP Semiconductors. 400 pF 400 pF BUFFER...
Page 58: Series Protection Resistors
46. Note that series resistors affect the s(max) output fall time. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 58 of 64...
Page 59: Input Leakage
Fig 47. Total HIGH-level input current as a function of the maximum value of R with supply voltage as a parameter UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 59 of 64...
Page 60: Wiring Pattern Of The Bus Lines
However, the shielded cable must have low capacitive coupling between the SDA and SCL lines to minimize crosstalk. UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 60 of 64...
Page 61: Abbreviations
Serial Peripheral Interface UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 61 of 64...
Page 62 NXP Semiconductors. damage, costs or problem which is based on any weakness or default in the In no event shall NXP Semiconductors be liable for any indirect, incidental, customer’s applications or products, or the application or use by customer’s punitive, special or consequential damages (including - without limitation - lost third party customer(s).
Page 63: Table Of Contents
C/SMBus compliancy ....32 continued >> UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. User manual Rev. 5 — 9 October 2012 63 of 64...
Page 64 ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 October 2012 Document identifier: UM10204...

NXP Semiconductors UM10204 User Manual

1 Introduction

2 C-Bus Features

3 The I C-Bus Protocol

4 Other Uses of the I C-Bus Communications Protocol

5 Bus Speeds

6 Electrical Specifications and Timing for I/O Stages and Bus Lines

7 Electrical Connections of I C-Bus Devices to the Bus Lines

8 Abbreviations

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