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Analog Devices Advantiv ADV7611 Hardware User's Manual
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Analog Devices Advantiv ADV7611 Hardware User's Manual

Analog Devices Advantiv ADV7611 Hardware User's Manual

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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Advantiv ADV7611 HDMI Receiver Functionality and Features
SCOPE
This user guide provides a detailed description of the Advantiv™ ADV7611 HDMI® receiver functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
XTALP
DPLL
XTALN
SCL
SDA
CEC
CEC
CONTROLLER
5V DETECT
RXA_5V
AND HPD
HPA_A/INT2*
CONTROLLER
EDID
DDCA_SDA
REPEATER
DDCA_SCL
CONTROLLER
PLL
RXA_C±
RXA_0±
EQUALIZER
RXA_1±
RXA_2±
*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR H PA_A/INT2.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
CONTROL
INTERFACE
I
2
C
CONTROL
AND DATA
HDCP
EEPROM
HDCP
EQUALIZER
ENGINE
Rev. A | Page 1 of 184
BACKEND
COLOR SPACE
CONVERSION
HDMI
PROCESSOR
COMPONENT
PROCESSOR
A
DATA
B
PREPROCESSOR
C
AND COLOR
SPACE
CONVERSION
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
Figure 1.
Hardware User Guide
12
12
12
INTERRUPT
CONTROLLER
(INT1, INT2)
MUTE
AUDIO
PROCESSOR
ADV7611
UG-180
P0 TO P7
P8 TO P15
P16 TO P23
LLC
HS
VS/FIELD/ALSB
DE
INT1
INT2*
AP
LRCLK
SCLK/INT2*
MCLK/INT2*

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Summary of Contents for Analog Devices Advantiv ADV7611

  • Page 1 DISCLAIMER Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.
  • Page 2 UG-180 Hardware User Guide TABLE OF CONTENTS     Scope ....................1 V_FREQ .................. 22     Disclaimer..................1 HDMI Decimation Modes ............22   Functional Block Diagram .............. 1 Primary Mode and Video Standard Configuration for   HDMI Free Run................22  ...
  • Page 3 Hardware User Guide UG-180     HDCP Ri Expired ..............42 Packets and InfoFrames Registers ..........67     HDMI Synchronization Parameters .........43 InfoFrames Registers ..............67     Notes ..................43 InfoFrame Collection Mode..........68     Horizontal Filter and Measurements ........43 InfoFrame Checksum Error Flags ........68  ...
  • Page 4 UG-180 Hardware User Guide     CP Gain Operation..............105 Initializing CEC Module ............. 148     Features of Manual Gain Control ........105 Using CEC Module as Initiator .......... 149     Features of Automatic Gain Control ......... 105 Using CEC Module as Follower .........
  • Page 5 Hardware User Guide UG-180     Appendix B ..................180 Appendix C ..................182     Recommended Unused Pin Configurations ......180 Pixel Output Formats ............... 182 REVISION HISTORY 12/11—Rev. 0 to Rev. A Added DLL Settings for 656, 8-/10-/12-Bit Modes Section ..27 Change to Video Output Formats Section ........
  • Page 6 UG-180 Hardware User Guide USING THE ADV7611 HARDWARE USER GUIDE NUMBER NOTATIONS Table 1. Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V).
  • Page 7 Hardware User Guide UG-180 Acronym/Abbreviation Description Inter integrated circuit. Key selection vector. Line locked clock. Least significant bit. L-PCM Linear pulse coded modulated. Mbps Megabit per second. MPEG Moving picture expert group. Millisecond. Most significant bit. No connect. One-time programmable. Pj’...
  • Page 8 UG-180 Hardware User Guide FIELD FUNCTION DESCRIPTIONS Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I C map, the register location within the I C map, and a detailed description of the field.
  • Page 9 Hardware User Guide UG-180 INTRODUCTION TO THE ADV7611 ® The ADV7611 is a high quality, single input, high definition multimedia interface (HDMI ) receiver. It incorporates an HDMI receiver that supports all mandatory HDMI 1.4a 3D TV formats up to 1080 p60@8-bit. It integrates a CEC controller that supports the capability discovery and control (CDC) feature.
  • Page 10 UG-180 Hardware User Guide Video Output Formats • Double data rate (DDR) 8-/12-bit 4:2:2 YCrCb • DDR supported only up to 50 MHz (an equivalent to ata rate clocked with 100 MHz clock in SDR mode) • Pseudo DDR (CCIR-656 type stream) 8-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P •...
  • Page 11 Hardware User Guide UG-180 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 HPA_A/INT2 PIN 1 CVDD VS/FIELD/ALSB RXA_C– RXA_C+ TVDD DVDDIO RXA_0– RXA_0+ ADV7611 TVDD TOP VIEW RXA_1–...
  • Page 12 UG-180 Hardware User Guide Pin No. Mnemonic Type Description Digital video output Line Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 162.5 MHz). Digital video output Video Pixel Output Port. Digital video output Video Pixel Output Port. Digital video output Video Pixel Output Port.
  • Page 13 Hardware User Guide UG-180 GLOBAL CONTROL REGISTERS The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7611. ADV7611 REVISION IDENTIFICATION RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only) Chip revision code.
  • Page 14 UG-180 Hardware User Guide CORE_PDN CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections: • CP block • Digital section of the HDMI block CORE_PDN, IO, Address 0x0B[1] A power-down control for the DPP, CP core, and digital sections of the HDMI core. Function CORE_PDN Description...
  • Page 15 Hardware User Guide UG-180 Entering Power-Down Mode 0 via Software The ADV7611 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This method allows an external processor to put the system in which the ADV7611 is integrated into standby mode. In this case, the CP and HDMI cores of the ADV7611 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0 through the POWER_DOWN bit.
  • Page 16 UG-180 Hardware User Guide TRI_PIX This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[23:0] is tristated. TRI_PIX, IO, Address 0x15[1] A control to tristate the pixel data on the pixel pins, P[23:0]. Function TRI_PIX Description...
  • Page 17 Hardware User Guide UG-180 Drive Strength Selection DR_STR It may be desirable to strengthen or weaken the drive strength of the output drivers for electromagnetic compatibility (EMC) and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes. The drive strenth DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals: •...
  • Page 18 UG-180 Hardware User Guide F_OUT_SEL, IO, Address 0x05[4] A control to select the DE or FIELD signal to be output on the DE pin. Function F_OUT_SEL Description 0 (default) Selects DE output on DE pin Selects FIELD output on DE pin Output Synchronization Signals Polarity INV_LLC_POL, IO Map, Address 0x06, [0] The polarity of the pixel clock provided by the ADV7611 via the LLC pin can be inverted using the INV_LLC_POL bit.
  • Page 19 Hardware User Guide UG-180 Digital Synthesizer Controls The ADV7611 features two digital encoder synthesizers that generate the following clocks: • Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent to HDMI streams.
  • Page 20 UG-180 Hardware User Guide PRIMARY MODE AND VIDEO STANDARD Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7611. There are two primary modes for the ADV7611: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with PRIM_MODE[3:0].
  • Page 21 Hardware User Guide UG-180 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment 0101 HDMI-COMP 000000 SD 1×1 525i 720 × 480 HDMI receiver support (Component video) 000001 SD 1×1 625i 720 × 576 000010 SD 2×1 525i 720 ×...
  • Page 22 UG-180 Hardware User Guide PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment 1010 Reserved xxxxxx Reserved Reserved 1011 Reserved xxxxxx Reserved Reserved 1100 Reserved xxxxxx Reserved Reserved 1101 Reserved xxxxxx Reserved Reserved 1110 Reserved xxxxxx Reserved Reserved 1111 Reserved xxxxxx...
  • Page 23 Hardware User Guide UG-180 RECOMMENDED SETTINGS FOR HDMI INPUTS This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection Video ID Code described in the 861 specification. Table 7 provides the recommended settings for the following registers: •...
  • Page 24 UG-180 Hardware User Guide Recommended Settings Recommended Settings if Free Run Not Used Video ID Codes Pixel if Free Run Used and or Free Run Used and (861 Specification) Formats Repetition DIS_AUTO_PARAM_BUFF = 0 DIS_AUTO_PARAM_BUFF = 1 SVGA 800 × 600p @ 56 PRIM_MODE = 0x6 PRIM_MODE = 0x6 VID_STD = 0x0...
  • Page 25 Hardware User Guide UG-180 PIXEL PORT CONFIGURATION The ADV7611 has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. The ADV7611 can provide output modes up to 24 bits. This section details the controls required to configure the ADV7611 pixel port. Appendix C contains tables describing pixel port configurations.
  • Page 26 UG-180 Hardware User Guide OP_SWAP_CB_CR, IO, Address 0x05[0] A control for the swapping of Cr and Cb data on the pixel buses. Function OP_SWAP_CB_CR Description 0 (default) Outputs Cr and Cb as per OP_FORMAT_SEL Inverts the order of Cb and Cr in the interleaved data stream OP_SWAP_CB_CR swaps the order in which Cb and Cr are interleaved in the output data stream.
  • Page 27 Hardware User Guide UG-180 LLC_DLL_PHASE[4:0], IO, Address 0x19[4:0] A control to adjust LLC DLL phase in increments of 1/32 of a clock period. Function LLC_DLL_PHASE[4:0] Description 00000 (default) Default xxxxx Sets one of 32 phases of DLL to vary LLC CLK DLL Settings for 656, 8-/10-/12-Bit Modes The following table shows the settings that must be used to enable 8-/10-/12-bit, 656 output.
  • Page 28 UG-180 Hardware User Guide HDMI RECEIVER HPA_A/INT2 5V DETECT AND HPA RXA_5V CONTROLLER TO INTERRUPT CONTROLLER DEEP COLOR CONVERSION CONTROLLER DATA TO DPP EDID/ TO DPP 4:2:2 TO 4:4:4 DDCA_SDA/DDCA_SC L REPEATER CONVERSION CONTROLLER TO DPP TO DPP HDCP EEPROM FILTER HDCP RXA_C±...
  • Page 29 Hardware User Guide UG-180 FILT_5V_DET_TIMER[6:0], Addr 68 (HDMI), Address 0x56[6:0] This control is used to set the timer for the digital glitch filter on the HDMI +5 V detect inputs. The unit of this parameter is two clock cycles of the ring oscillator (~ 47 ns). The input must be constantly high for the duration of the timer; otherwise, the filter output remains low.
  • Page 30 UG-180 Hardware User Guide HPA_AUTO_INT_EDID[1:0], Addr 68 (HDMI), Address 0x6C[2:1] This control selects the type of automatic control on the HPA output pins. This bit has no effect when HPA_MANUAL is set to 1. Function HPA_AUTO_INT_EDID[1:0] Description HPA of an HDMI port asserted high immediately after internal EDID activated for that port. HPA of a specific HDMI port deasserted low immediately after internal E-EDID is de-activated for that port.
  • Page 31 Hardware User Guide UG-180 HPA_OVR_TERM, Addr 68 (HDMI), Address 0x6C[3] A control to set the termination control to be overridden by the HPA setting. When this bit is set, termination on a specific port is set according to the HPA status of that port. Function HPA_OVR_TERM Description...
  • Page 32 UG-180 Hardware User Guide Notes • If the internal E-EDID RAM is enabled, an external E-EDID storage device must not be connected on the DDC bus of that port. • The internal E-EDID can be read by current address read sequences on the DDC port. •...
  • Page 33 Hardware User Guide UG-180 PORT A E-EDID STRUCTURE 0x1FF BLOCK 2 CHECKSUM 0x1FE BLOCK 3 0x180 0x17F BLOCK 2 CHECKSUM 0x17E BLOCK 2 0x100 0xFF BLOCK 1 CHECKSUM 0xFE BLOCK 1 0x80 0x7F BLOCK 0 CHECKSUM 0x7E BLOCK 0 0x00 Figure 4.
  • Page 34 UG-180 Hardware User Guide TMDS_CLK_A_RAW, IO, Address 0x6A[4] (Read Only) Raw status of Port A TMDS clock detection signal. Function TMDS_CLK_A_RAW Description 0 (default) No TMDS clock detected on Port A TMDS clock detected on Port A Important • The clock detection flag is valid if the part is powered up or in Power Down Mode 1. Refer to the Power-Down Mode 1 section.
  • Page 35 Hardware User Guide UG-180 Function VIDEO_3D_RAW Description Video 3D not detected (read only) Video 3D detected TMDS MEASUREMENT The ADV7611 contains logic that measures the frequency of the TMDS clock transmitted. The TMDS frequency can be read back via the TMDSFREQ[8:0] and TMDSFREQ_FRAC[6:0] registers.
  • Page 36 UG-180 Hardware User Guide NEW_TMDS_FRQ_RAW , IO, Address 0x83[1] (Read Only) Status of new TMDS frequency interrupt signal. When set to 1, it indicates the TMDS Frequency has changed by more than the tolerance set in FREQTOLERANCE[3:0]. Once set, this bit will remain high until it is cleared via NEW_TMDS_FREQ_CLR. Function NEW_TMDS_FRQ_RAW Description...
  • Page 37 Hardware User Guide UG-180 TMDS TMDS CLOCK DPLL DIVIDER TMDS CH0 TMDS CHANNEL 0 TMDS SAMPLING TMDS CH1 TMDS FIFO TMDS DECODING DATA CHANNEL 1 RECOVERY TMDS CH2 TMDS CHANNEL 2 Figure 5. HDMI Video FIFO The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are about to point to the same location.
  • Page 38 UG-180 Hardware User Guide DCFIFO_KILL_DIS , Addr 68 (HDMI), Address 0x1B[2] The video FIFO output is zeroed if there is more than one resynchronization of the pointers within two FIFO cycles. This behavior can be disabled with this bit. Function DCFIFO_KILL_DIS Description 0 (default)
  • Page 39 Hardware User Guide UG-180 DEREP_N_OVERRIDE , Addr 68 (HDMI), Address 0x41[4] This control allows the user to override the pixel repetition factor. The ADV7611 then uses DEREP_N instead of HDMI_PIXEL_REPETITION[3:0] to discard video pixel data from the incoming HDMI stream. Function DEREP_N_OVERRIDE Description...
  • Page 40 UG-180 Hardware User Guide HDMI_CONTENT_ENCRYPTED , Addr 68 (HDMI), Address 0x05[6] (Read Only) A readback to indicate the use of HDCP encryption. Function HDMI_CONTENT_ENCRYPTED Description 0 (default) The input stream processed by the HDMI core is not HDCP encrypted. The input stream processed by the HDMI core is HDCP encrypted. HDMI_ENCRPT_X_RAW reports the encryption status of the data present on each individual HDMI port (where X = A).
  • Page 41 Hardware User Guide UG-180 START (AFTER POWER-UP) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV AND CHECKSUM CS1 FROM HDCP OTP ROM DERIVE CHECKSUM CS1' FROM KSV HDCP_KEY_ERROR = 1 CS1 = CS1' SET BKSV (HDCP REGISTER ADDRESS 0x00 BKSV = KSV HDCP_KEY_READ = 1 HDCP_KEY_ERROR = 0 Figure 6.
  • Page 42 UG-180 Hardware User Guide START (AKSV UPDATE FROM TRANSMITTER) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV, HDCP KEYS AND CHECKSUM CS2 FROM HDCP PROM DERIVE CHECKSUM CS2' FROM KSV AND HDCP KEYS HDCP_KEY_ERROR = 1 CS1 = CS1' DERIVE LINK VERIFICATION Ri' UPDATE BKSV AND Ri' IN HDCP RESGISTERS HDCP_KEY_READ = 1...
  • Page 43 Hardware User Guide UG-180 HDMI SYNCHRONIZATION PARAMETERS The ADV7611 contains the logic required to measure the details of the incoming video resolution. The HDMI synchronization parameters readback registers from the HDMI Map can be used, in addition to the STDI registers from the CP (refer to the Standard Detection and Identification section), to estimate the video resolution of the incoming HDMI stream.
  • Page 44 UG-180 Hardware User Guide TOTAL_LINE_WIDTH[13:0] , Addr 68 (HDMI), Address 0x1E[5:0]; Address 0x1F[7:0] (Read Only) Total line width is a horizontal synchronization measurement. This gives the total number of pixels per line. This measurement is valid only when the DE regeneration filter has locked. Function TOTAL_LINE_WIDTH[13:0] Description...
  • Page 45 Hardware User Guide UG-180 DATA ENABLE HSYNC NOTE: TOTAL NUMBER OF PIXELS PER LINE ACTIVE NUMBER OF PIXELS PER LINE HSYNC FRONT PORCH WIDTH IN PIXEL UNIT HSYNC WIDTH IN PIXEL UNIT HSYNC BACK PORCH WIDTH IN PIXEL UNIT Figure 8. Horizontal Timing Parameters Horizontal Filter Locking Mechanism The locking/unlocking mechanism of the HDMI horizontal filter is as follows: •...
  • Page 46 UG-180 Hardware User Guide FIELD0_TOTAL_HEIGHT[13:0] , Addr 68 (HDMI), Address 0x26[5:0]; Address 0x27[7:0] (Read Only) Field 0 total height is a vertical synchronization measurement. This readback gives the total number of half lines in Field 0. This measurement is valid only when the vertical filter has locked. Function FIELD0_TOTAL_HEIGHT[13:0] Description...
  • Page 47 Hardware User Guide UG-180 DATA ENABLE HSYNC VSYNC NOTE: TOTAL NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. ACTIVES NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. VSYNC FRONT PORCH WIDTH IN FIELD 0. UNIT IS IN HALF LINES. VSYNC PULSE WIDTH IN FIELD 0.
  • Page 48 UG-180 Hardware User Guide DATA ENABLE HSYNC VSYNC NOTE: TOTAL NUMBER OF LINES IN FIELD 1. UNIT IS IN HALF LINES. ACTIVES NUMBER OF LINES IN FIELD 1. UNIT IS IN HALF LINES. VSYNC FRONT PORCH WIDTH IN FIELD 1. UNIT IS IN HALF LINES. VSYNC PULSE WIDTH IN FIELD 1.
  • Page 49 Hardware User Guide UG-180 Audio DPLL The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs. The audio master clock is used to clock the audio processing section. Locking Mechanism When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL locks within two cycles of the audio master clock after the following two conditions are met:...
  • Page 50 UG-180 Hardware User Guide ADDRESS ORDER EMPTY ADDRESS 63 … … … WRITE POINTER EMPTY ADDRESS N + 2 STEREO DATA N – 1 ADDRESS N + 1 STEREO DATA N – 2 ADDRESS N … … … STEREO DATA 1 ADDRESS 3 READ POINTER STEREO DATA 0...
  • Page 51 Hardware User Guide UG-180 Function FIFO_NEAR_OVFL_RAW Description 0 (default) Audio FIFO has not reached high threshold defined in AUDIO_FIFO_ALMOST_FULL_THRESHOLD [5:0] Audio FIFO has reached high threshold defined in AUDIO_FIFO_ALMOST_FULL_THRESHOLD [5:0] AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD[6:0] , Addr 68 (HDMI), Address 0x12[6:0] Sets the threshold used for FIFO_NEAR_UFLO_RAW. FIFO_NEAR_UFLO_ST interrupt is triggered if audio FIFO goes below this level. Function AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD[6:0] Description...
  • Page 52 UG-180 Hardware User Guide DST_AUDIO_PCKT_DET , Addr 68 (HDMI), Address 0x18[2] (Read Only) DST audio packet detection bit. This bit resets to zero on the 11th HSync leading edge following a DST packet if a subsequent DST has not been received. Or if an audio, DSD, or HBR packet sample packet has been received or after an HDMI reset condition. Function DST_AUDIO_PCKT_DET Description...
  • Page 53 Hardware User Guide UG-180 START ENABLE THE AUDIO_MODE_CHNG_ST INTERRUPT AUDIO_MODE_CH NG_ST INTERRUPT? SET AUDIO_MODE_CHNG_CLR TO 1 NO AUDIO SAMPLE PACKETS ARE AUDIO SAMPLE PACKETS ARE AUDIO_SAMPLE BEING RECEIVED BEING RECEIVED PCKT_DET? NO DSD PACKETS ARE DSD PACKETS ARE BEING RECEIVED BEING RECEIVED DSD_PACKET_DET? NO DST PACKETS ARE...
  • Page 54 UG-180 Hardware User Guide MUX_SPDIF_TO_I2S_ENABLE , Addr 68 (HDMI), Address 0x6E[3] Enables muxing SPDF data into I S pins (AP) Function MUX_SPDIF_TO_I2S_ENABLE Description 0 (default) Don’t modify I2S outputs Mux SPDIF into I2S pins S/SPDIF Audio Interface and Output Controls Two controls are provided to change the mapping between the audio output ports and the I S and SPDIF (IEC60958) signals.
  • Page 55 Hardware User Guide UG-180 Notes • I2SOUTMODE is effective when the ADV7611 is configured to output I S streams or AES3 streams. This is the case in the situation where the ADV7611 receives audio sample packets The following audio formats can be output when the ADV7611 receives audio sample packets: •...
  • Page 56 UG-180 Hardware User Guide LEFT RIGHT MSB – 1 MSB – 1 MSB EXTENDED MSB EXTENDED 32 CLOCK SLOTS 32 CLOCK SLOTS Figure 15. Timing Audio Data Output in Right Justified Mode LEFT RIGHT 32 CLOCK SLOTS 32 CLOCK SLOTS Figure 16.
  • Page 57 Hardware User Guide UG-180 CHANNEL A CHANNEL B 32 CLOCK SLOTS 32 CLOCK SLOTS FRAME N FRAME N + 1 Figure 19. AES3 Stream Timing Diagram LRCLK 256 SCLKs SCLK 32 SCLKs SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7...
  • Page 58 UG-180 Hardware User Guide AUDIO CHANNEL MODE AUDIO_CH_MD_RAW indicates if 2-channel audio data or multichannel audio data is received. AUDIO_CH_MD_RAW , IO, Address 0x65[4] (Read Only) Raw status signal indicating the layout value of the audio packets that were last received. Function AUDIO_CH_MD_RAW Description...
  • Page 59 Hardware User Guide UG-180 Audio Mute Configuration The ADV7611 can be configured to automatically mute an L-PCM audio stream when selectable mute conditions occur. The audio muting is configured as follows: • Set the audio muting speed via AUDIO_MUTE_SPEED[4:0]. • Set NOT_AUTO_UNMUTE, as follows: •...
  • Page 60 UG-180 Hardware User Guide NOT_AUTO_UNMUTE , Addr 68 (HDMI), Address 0x1A[0] A control to disable the auto unmute feature. When set to 1, audio can be unmuted manually if all mute conditions are inactive by setting NOT_AUTO_UNMUTE to 0 and then back to 1. Function NOT_AUTO_UNMUTE Description...
  • Page 61 Hardware User Guide UG-180 Internal Mute Status The internal mute status is provided through the INTERNAL_MUTE_RAW bit. INTERNAL_MUTE_RAW, IO, Address 0x65[6] (Read Only) Raw status signal of internal mute signal. Function INTERNAL_MUTE_RAW Description 0 (default) Audio is not muted Audio is muted AV Mute Status AV_MUTE, Addr 68 (HDMI), Address 0x04[6] (Read Only) Readback of AVMUTE status received in the last general control packet received.
  • Page 62 UG-180 Hardware User Guide Audio Stream with Incorrect Parity Error The ADV7611 discards audio sample packets that have an incorrect parity bit. When these samples are received, the ADV7611 repeats the previous audio sample with a valid parity bit. The audio stream out of the ADV7611 can be muted in this situation if the audio mute mask MT_MSK_PARITY_ERR is set.
  • Page 63 Hardware User Guide UG-180 CHANGE_N_RAW , IO, Address 0x7E[3] (Read Only) Status of the ACR N Value changed interrupt signal. When set to 1 it indicates the N Value of the ACR packets has changed. Once set, this bit will remain high until it is cleared via CHANGE_N_CLR. Function CHANGE_N_RAW Description...
  • Page 64 UG-180 Hardware User Guide START ENABLE THE CS_DATA_VALID_ST INITIALIZATION INTERRUPT CS_DATA_VALID_S T SET TO 1? CHECK IF THE CS_DATA_VALID SET CS_DATA_VALID_CLR TO 1 INTERRUPT HAS TRIGGERED CS_DATA_VALID_R AW SET TO 1? READ THE CHANNEL STATUS BITS IN THE CHANNEL STATUS BITS PREVIOUSLY HDMI MAP 0x36 TO 0x3A READ ARE NOT VALID CS_DATA_VALID_S...
  • Page 65 Hardware User Guide UG-180 CS_DATA[1] , PCM/non-PCM Audio Sample, HDMI Map, Address 0x36[1] Function CS_DATA[1] Description 0 (default) Audio sample word represents linear PCM samples Audio sample word used for other purposes CS_DATA[2] , Copyright, HDMI Map, Address 0x36[2] Function CS_DATA[2] Description 0 (default)
  • Page 66 UG-180 Hardware User Guide Sampling and Frequency Accuracy The sampling frequency and clock accuracy are specified by Byte 3 of the channel status. For additional information, refer to the IEC60958 standards. CS_DATA[27:24] , Sampling Frequency, HDMI Map, Address 0x39[3:0] Function CS_DATA[27:24] Description 0000 (default)
  • Page 67 Hardware User Guide UG-180 Channel Status Copyright Value Assertion It is possible to overwrite the copyright value of the channel status bit that is passed to the SPDIF output. This is done via the CS_COPYRIGHT_MANUAL CS_COPYRIGHT_VALUE controls. CS_COPYRIGHT_MANUAL , Addr 68 (HDMI), Address 0x50[1] A control to select automatic or manual setting of the copyright value of the channel status bit that is passed to the SPDIF output.
  • Page 68 UG-180 Hardware User Guide InfoFrame Collection Mode The ADV7611 has two modes for storing the InfoFrame packet sent from the source into the internal memory. By default, the ADV7611 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame. The ADV7611 also provides a mode to store every InfoFrame sent from the source, regardless of a InfoFrame packet checksum error.
  • Page 69 Hardware User Guide UG-180 VS_INF_CKS_ERR_RAW , IO, Address 0x8D[0] (Read Only) Status of vendor specific InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an Vendor Specific InfoFrame. Once set, this bit will remain high until it is cleared via VS_INF_CKS_ERR_CLR. Function VS_INF_CKS_ERR_RAW Description...
  • Page 70 UG-180 Hardware User Guide Audio InfoFrame Registers Table 15 provides the list of readback registers available for the Audio InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the audio InfoFrame fields. Table 15. Audio InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 71 Hardware User Guide UG-180 SPD InfoFrame Registers Table 16 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 16. SPD InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 72 UG-180 Hardware User Guide MPEG Source InfoFrame Registers Table 17 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 17. MPEG InfoFrame Registers InfoFrame Map Address Access Type Register Name...
  • Page 73 Hardware User Guide UG-180 Vendor Specific InfoFrame Registers Table 18 provides a list of readback registers available for the vendor specific InfoFrame. Table 18. VS InfoFrame Registers InfoFrame Map Address Register Name Byte Name 0xEC VS_PACKET_ID[7:0] Packet type value 0xED VS_INF_VERS InfoFrame version number 0xEE...
  • Page 74 UG-180 Hardware User Guide PACKET REGISTERS ACP Packet Registers Table 19 provides the list of readback registers available for the ACP packets. Refer to the HDMI specifications for a detailed explanation of the ACP packet fields. Table 19. ACP Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 75 Hardware User Guide UG-180 ISRC Packet Registers Table 20 and Table 21 provide lists of readback registers available for the ISRC packets. Refer to the HDMI specifications for a detailed explanation of the ISRC packet fields. Table 20. ISRC1 Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 76 UG-180 Hardware User Guide The ISRC1 packet registers are considered valid if ISRC1_PCKT_RAW is set to 1. ISRC1_PCKT_RAW , IO, Address 0x60[6] (Read Only) Raw status signal of International Standard Recording Code 1 (ISRC1) packet detection signal. Function ISRC1_PCKT_RAW Description 0 (default) No ISRC1 packets received since the last HDMI packet detection reset.
  • Page 77 Hardware User Guide UG-180 Gamut Metadata Packets Refer to the HDMI specifications for a detailed explanation of the gamut metadata packet fields. Table 22. Gamut Metadata Packet Registers HDMI Map Address Register Name Packet Byte No. 0xF8 GAMUT_PACKET_ID[7:0] Packet type value 0xF9 GAMUT_HEADER1 0xFA...
  • Page 78 UG-180 Hardware User Guide CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS The packet type value of each set of packet and InfoFrame registers in the InfoFrame Map is programmable. This allows the user to configure the ADV7611 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port.
  • Page 79 Hardware User Guide UG-180 ISRC1_PACKET_ID[7:0] , Addr 7C (InfoFrame), Address 0xF2[7:0] ISRC1 InfoFrame ID. Function ISRC1_PACKET_ID[7:0] Description 0xxxxxxx Packet type value of packet stored in InfoFrame map, Address 0x8C to 0xA7 1xxxxxxx Packet type value of InfoFrame stored in InfoFrame map, Address 0x8C to 0xA7 ISRC2_PACKET_ID[7:0] , Addr 7C (InfoFrame), Address 0xF5[7:0] ISRC2 InfoFrame ID.
  • Page 80 UG-180 Hardware User Guide When KSV_LIST_READY is set to 1, the EDID/repeater controller computes the SHA-1 hash value V’ , updates the corresponding V’ registers (refer to Table 24), and sets the READY bit (that is, BCAPS[5]) to 1. This indicates to the transmitter attached to the ADV7611 that the KSV FIFO and SHA-1 hash value V’...
  • Page 81 Hardware User Guide UG-180 AKSV_UPDATE_A_RAW , IO, Address 0x88[0] (Read Only) Status of Port A AKSV update interrupt signal. When set to 1 it indicates that transmitter has written its AKSV into HDCP registers for Port A. Once set, this bit will remain high until it is cleared via AKSV_UPDATE_A_CLR. Function AKSV_UPDATE_A_RAW Description...
  • Page 82 UG-180 Hardware User Guide BCAPS[7:0] , Addr 64 (Repeater), Address 0x40[7:0] This is the BCAPS register presented to the Tx attached to the active HDMI port. Function BCAPS[7:0] Description 10000011 (default) Default BCAPS register value presented to the Tx xxxxxxxx BCAPS register value presented to the Tx BSTATUS[15:0] , Addr 64 (Repeater), Address 0x42[7:0];...
  • Page 83 Hardware User Guide UG-180 KSV_MAP_SELECT[2:0] , Addr 64 (Repeater), Address 0x79[6:4] Selects which 128 bytes of KSV list will be accessed when reading or writing to addresses 0x80 to 0xFF in this map. Values from 5 and upwards are not valid. Function KSV_MAP_SELECT[2:0] Description...
  • Page 84 UG-180 Hardware User Guide KSV Byte Number Register Name Register Addresses KSV_BYTE_38[7:0] 0xA6[7:0] KSV_BYTE_39[7:0] 0xA7[7:0] KSV_BYTE_40[7:0] 0xA8[7:0] KSV_BYTE_41[7:0] 0xA9[7:0] KSV_BYTE_42[7:0] 0xAA[7:0] KSV_BYTE_43[7:0] 0xAB[7:0] KSV_BYTE_44[7:0] 0xAC[7:0] KSV_BYTE_45[7:0] 0xAD[7:0] KSV_BYTE_46[7:0] 0xAE[7:0] KSV_BYTE_47[7:0] 0xAF[7:0] KSV_BYTE_48[7:0] 0xB0[7:0] KSV_BYTE_49[7:0] 0xB1[7:0] KSV_BYTE_50[7:0] 0xB2[7:0] KSV_BYTE_51[7:0] 0xB3[7:0] KSV_BYTE_52[7:0] 0xB4[7:0] KSV_BYTE_53[7:0] 0xB5[7:0]...
  • Page 85 Hardware User Guide UG-180 KSV Byte Number Register Name Register Addresses KSV_BYTE_91[7:0] 0xDB[7:0] KSV_BYTE_92[7:0] 0xDC[7:0] KSV_BYTE_93[7:0] 0xDD[7:0] KSV_BYTE_94[7:0] 0xDE[7:0] KSV_BYTE_95[7:0] 0xDF[7:0] KSV_BYTE_96[7:0] 0xE0[7:0] KSV_BYTE_97[7:0] 0xE1[7:0] KSV_BYTE_98[7:0] 0xE2[7:0] KSV_BYTE_99[7:0] 0xE3[7:0] KSV_BYTE_100[7:0] 0xE4[7:0] KSV_BYTE_101[7:0] 0xE5[7:0] KSV_BYTE_102[7:0] 0xE6[7:0] KSV_BYTE_103[7:0] 0xE7[7:0] KSV_BYTE_104[7:0] 0xE8[7:0] KSV_BYTE_105[7:0] 0xE9[7:0] KSV_BYTE_106[7:0] 0xEA[7:0]...
  • Page 86 UG-180 Hardware User Guide Register Name Address Location Function 0x2D[7:0]: SHA_D[15:8] 0x2E[7:0]: SHA_D[23:16] 0x2F[7:0]: SHA_D[31:24] SHA_E[31:0] 0x30[7:0]: SHA_E[7:0] H4 part of SHA-1 hash value V’ . Register also called (V’ . H4) 0x31[7:0]: SHA_E[15:8] 0x32[7:0]: SHA_E[23:16] 0x33[7:0]: SHA_E[31:24] All registers specified in Table 24 are located in the repeater map. Refer to HDCP protection system Standards.
  • Page 87 Hardware User Guide UG-180 UP_CONVERSION_MODE , Addr 68 (HDMI), Address 0x1D[5] A control to select linear or interpolated 4:2:2 to 4:4:4 conversion. A 4:2:2 incoming stream is upconverted to a 4:4:4 stream before being sent to the CP. Function UP_CONVERSION_MODE Description 0 (default) Cr and Cb samples are repeated in their respective channel...
  • Page 88 UG-180 Hardware User Guide DPP_BYPASS_EN , Addr 44 (CP), Address 0xBD[4] Manual control to enable DPP block. Function DPP_BYPASS_EN Description 1 (default) DPP bypassed DPP enabled COLOR SPACE INFORMATION SENT TO THE DPP AND CP SECTIONS The HDMI section sends information regarding the color space of the video it outputs to the DPP and the CP sections. This color space information is derived from the DVI/HDMI status of the input stream the HDMI section processes and from the AVI InfoFrame that the HDMI section decodes from the input stream.
  • Page 89 Hardware User Guide UG-180 Table 26. HDMI Flags in IO Map Register 0x65 Bit Name Bit Position Description GAMUT_MDATA_RAW 0 (LSB) Returns 1 if a Gamut Metadata packet was received. For additional information, see the Gamut Metadata Packets section. AUDIO_C_PCKT_RAW Returns 1 if an audio clock regeneration packet has been received.
  • Page 90 UG-180 Hardware User Guide Table 30. HDMI Flags in IO Map Register 0x7E Bit Name Bit Position Description NEW_GAMUT_MDATA_RAW 0 (LSB) When set to 1 indicates that a gamut metadata packet with new content has been received. Once set, this bit remains high until the interrupt is cleared via NEW_GAMUT_ MDATA_PCKT_CLR.
  • Page 91 Hardware User Guide UG-180 Table 32. HDMI InfoFrame Checksum Error Flags in IO Map Bit Name IO Map Location Description AVI_INF_CKS_ERR_RAW 0x88[4] Description available in the InfoFrame Checksum Error Flags section AUD_INF_CKS_ERR_RAW 0x88[5] Description available in the InfoFrame Checksum Error Flags section SPD_INF_CKS_ERR_RAW 0x88[6] Description available in the InfoFrame Checksum Error Flags section...
  • Page 92 UG-180 Hardware User Guide DATA PREPROCESSOR AND COLOR SPACE CONVERSION AND COLOR CONTROLS COLOR SPACE CONVERSION MATRIX The ADV7611 provides any-to-any color space support. It supports formats such as RGB, YUV, YCbCr and many other color spaces. The ADV7611 features a 3×3 CSC in the CP block (CP CSC), as shown in Figure 26. The CP CSC also provides color controls for brightness, contrast, saturation and hue adjustments.
  • Page 93 Hardware User Guide UG-180 Selecting Auto or Manual CP CSC Conversion Mode The ADV7611 CP CSC provides two modes for the CSC configuration: automatic CSC mode and manual CSC mode. In automatic CSC mode, the user is required to program the input color space and the output color space for the correct operation of the CSC matrix.
  • Page 94 UG-180 Hardware User Guide RGB_OUT , IO, Address 0x02[1] A control to select output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. It is used in conjunction with the INP_COLOR_SPACE[3:0] and ALT_GAMMA bits to select the applied CSC. Function RGB_OUT Description...
  • Page 95 Hardware User Guide UG-180 HDMI Automatic CSC Operation In HDMI mode, the ADV7611 provides an automatic CSC function based on the AVI InfoFrame sent from the source. The flowchart in Figure 28 shows the mechanism of the ADV7611 auto CSC functionality in HDMI mode. Note: In the following flowcharts, a red dashed line represents a state that is undefined according to the CEA-861D specification, and therefore should never happen.
  • Page 96 UG-180 Hardware User Guide Y[1:0] = 01b, 10b, 11b YCbCr MODE START YCbCr COLORIMETRY C[1:0] = xxb? C[1:0] = 10b C[1:0] = 10b C[1:0] = 00b C[1:0] = 11b YUV709 YUV601 EXTENDED COLORIMETRY EC[2:0] = xxxb? EC[2:0] = 001b EC[2:0] = 000b EC[2:0] != (001 OR 000) xvYCC709 xvYCC601...
  • Page 97 Hardware User Guide UG-180 Y[1:0] = 00b RGB 4:4:4 MODE START DETECT QUANTIZATION RANGE Q[1:0] = xxb? Q[1:0] = 01b Q[1:0] = 00b Q[1:0] = 10b QZERO_RGB_FULL = 0 QZERO_RGB_FULL = 1 (DEFAULT) 1-BIT CONTROL TO SELECT FULL/LIMITED RGB/RANGE RGB LIMITED RANGE RGB FULL RANGE Figure 32.
  • Page 98 UG-180 Hardware User Guide CSC_SCALE A1[12:0] A4[12:0] ×2 OUT_A[11:0] IN_A[11:0] × A2[12:0] IN_B[11:0] × A3[12:0] IN_C[11:0] × Figure 33. Single CSC Channel The coefficients mentioned previously are detailed in Table 38 along with the default values for these coefficients. Table 38. CSC Coefficients Function Bit CP Map Address Reset Value (Hex)
  • Page 99 Hardware User Guide UG-180 CSC Manual Programming The equations performed by the CP CSC are as follows: CSC Channel A ⎡ ⎤ × × × × scale ⎢ ⎣ ⎥ ⎦ 4096 4096 4096 CSC Channel B ⎡ ⎤ × ×...
  • Page 100 UG-180 Hardware User Guide The ranges of the three equations are shown in Table 39. Table 39. Equation Ranges Equation Minimum Value Maximum Value Range 0 + 0 + 0 = 0 0.59 + 0.3 + 0.11 = 1 [0 … 1] = 1 (−0.34) + (−0.17) = −0.51 0.51 [−0.51 …+ 0.51] = 1.02...
  • Page 101 Hardware User Guide UG-180 CSC in Pass-Through Mode It is possible to configure the CP CSC in a pass-through mode. In this mode, the CP CSC is used but does not alter the data it processes. The CP CSC pass-through mode is obtained using the following settings: MAN_CP_CSC_EN to 1’b1.
  • Page 102 UG-180 Hardware User Guide CP_BRIGHTNESS[7:0] , Addr 44 (CP), Address 0x3C[7:0] A control to set the brightness. This field is a signed value. The effective brightness value applied to the luma is obtained by multiplying the programmed value CP_BRIGHTNESS with a gain of 4. The brightness applied to the luma has a range of [−512 to +508]. This control is functional if VID_ADJ_EN is set to 1.
  • Page 103 Hardware User Guide UG-180 COMPONENT PROCESSOR COMPONENT PROCESSING STANDARD SYNC PROCESSING IDENTIFICATION CHANNEL (STDI) HS/VS/F SYNC EXTRACTOR OUTPUT VIDEO DATA CHA, CHB, AND CHC OUTPUT MEASUREMENT DIGITAL VIDEO DATA BLOCK (≥I GAIN OFFSET AV CODE DELAY FINE CHA, CHB, AND CP CSC CONTROL ADDER...
  • Page 104 UG-180 Hardware User Guide CLMP_FREEZE , Addr 44 (CP), Address 0x6C[5] Stops the digital fine clamp loops for Channel A, Channel B, and Channel C from updating. Function CLMP_FREEZE Description 0 (default) Clamp value updated on every active video line Clamp loops are stopped and not updated CLMP_A_MAN , Addr 44 (CP), Address 0x6C[7] Manual clamping enable for Channel A.
  • Page 105 Hardware User Guide UG-180 CLMP_C[11:0] , Addr 44 (CP), Address 0x6F[3:0]; Address 0x70[7:0] Manual clamp value for Channel C. This field is an unsigned 12-bit value to be subtracted from the incoming video signal. This value programmed in this register is effective if the CLMP_BC_MAN is set to 1. To change the CLMP_C[11:0], Register Address 0x6F and Register Address 0x70 must be updated with the desired clamp value written to in this order and with no other I C access in between.
  • Page 106 UG-180 Hardware User Guide AGC_MODE_MAN GAIN_MAN HDMI_MODE SSPD DETECTED EMBEDDED SYNCS?? INPUT GAIN GAIN OP_656_RANGE OP_656_RANGE SET GAIN BASED ON RANGE A/B/C_GAIN[9:0] VALUE (255 – 0 + 1) × 0 (0 TO 255 OUTPUT) 0 (0 TO 255 OUTPUT) 16/1344 = 3.047 0 TO 255 1 (16 TO 235 Y/RGB (235 –...
  • Page 107 Hardware User Guide UG-180 A_GAIN[9:0] , Addr 44 (CP), Address 0x73[5:0]; Address 0x74[7:4] A control to set the manual gain value for Channel A. This register is an unsigned value in a 2.8 binary format. To change A_GAIN[9:0], the register at Address 0x73 and Address 0x74 must be written to in this order with no I C access in between.
  • Page 108 UG-180 Hardware User Guide Manual Gain Filter Mode The ADV7611 provides a special filter option for the manual gain mode. This is functional only when manual gain is enabled. The purpose of this filter is a smoothing mechanism when the manual gain value is updated continuously by an external system based on either external or readback conditions in the ADV7611.
  • Page 109 Hardware User Guide UG-180 ALT_DATA_SAT , IO, Address 0x02[0] A control to disable the data saturator that limits the output range independently of OP_656_RANGE. This bit is used to support extended data range modes. Function ALT_DATA_SAT Description 0 (default) Data saturator enabled or disabled according to OP_656_RANGE setting Reverses OP_656_RANGE decision to enable or disable the data saturator CP OFFSET BLOCK The offset block consists of three independent adders, one for each channel.
  • Page 110 UG-180 Hardware User Guide A_OFFSET[9:0] , Addr 44 (CP), Address 0x77[5:0]; Address 0x78[7:4] A control to set the manual offset for Channel A. This field stores an unsigned value. To change A_OFFSET[9:0], Register Address 0x77 and Register Address 0x78 must be written to in this order with no I C access in between.
  • Page 111 Hardware User Guide UG-180 AVCODE_INSERT_EN , IO, Address 0x05[2] A control to select AV code insertion into the data stream. Function AVCODE_INSERT_EN Description Does not insert AV codes into data stream 1 (default) Inserts AV codes into data stream AV_POS_SEL , Addr 44 (CP), Address 0x7B[2] A control to select AV codes position.
  • Page 112 UG-180 Hardware User Guide REPL_AV_CODE = 0 REPL_AV_CODE = 1 CHANNEL A CHANNEL B CHANNEL C AV CODE SECTION AV CODE SECTION Figure 37. AV Code Output Options (CP) SWAP_SPLIT_AV , Addr 44 (CP), Address 0xC9[2] A control to swap the luma and chroma AV codes in DDR modes. Function SWAP_SPLIT_AV Description...
  • Page 113 Hardware User Guide UG-180 HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLMP_A[11:0] CLAMP RGB_OUT 12-BIT CLMP_A_MAN 12'd0 HDMI_CLMP_ENABLE AUTO VALUE 12'd2056 (16 @ 8-BIT) AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN A_GAIN[9:0] CP_OP_656_SEL* × × 10'd220 (×0.86) GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)
  • Page 114 UG-180 Hardware User Guide HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLMP_B[11:0]/CLMP_C[11:0] CLAMP RGB_OUT 12-BIT CLMP_BC_MAN 12'd0 HDMI_CLMP_ENABLE 12'd2048 (128 @ 8-BIT) AUTO VALUE AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN B_GAIN[9:0]/C_GAIN[9:0] CP_OP_656_SEL* 10'd220 (×0.86) × × GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)
  • Page 115 Hardware User Guide UG-180 SYNC PROCESSED BY CP SECTION The CP Core uses the HDMI section as its source of HSync, VSync and DE. Sync Routing from HDMI Section The CP section receives syncs from the HDMI section, as shown in Figure 40. PRIM_MODE[2] HS 1 HDMI HS...
  • Page 116 UG-180 Hardware User Guide In ADV7611, there are three operational modes for the STDI block: • Continuous mode: The STDI block performs continuous measurements on lock/unlock bases and updates the corresponding I C registers based on the lock status bit (STDI_DVALID). •...
  • Page 117 Hardware User Guide UG-180 CH1_STDI_DVALID, Addr 44 (CP), Address 0xB1[7] (Read Only) This bit is set when the measurements performed by Sync Channel 1 STDI are completed. High level signals validity for CH1_BL, CH1_LCF, CH1_LCVS, CH1_FCL, and CH1_STDI_INTLCD parameters. To prevent false readouts, especially during signal acquisition, CH1_SDTI_DVALID only goes high after four fields with same length are recorded.
  • Page 118 UG-180 Hardware User Guide Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism STDI Horizontal Locking Operation For the STDI horizontal locking operation, the STDI block compares adjacent line length differences (in XTAL clock cycles) with the programmed threshold. If 128 consecutive adjacent lines lengths are within the threshold, the STDI horizontally locks to the incoming video.
  • Page 119 Hardware User Guide UG-180 FIELD2 – FIELD3 ≤ THRESHOLD? FIELD4 – FIELD5 ≤ THRESHOLD? FIELD1 – FIELD2 ≤ THRESHOLD? FIELD3 – FIELD4 ≤ THRESHOLD? FIELD 1 FIELD 2 FIELD 3 FIELD 4 FIELD 5 FIELD 6 ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO...
  • Page 120 UG-180 Hardware User Guide CH1_FCL[12:0] , Addr 44 (CP), Address 0xB8[4:0]; Address 0xB9[7:0] (Read Only) A readback for the Sync Channel 1 field count length. Number of crystal clock cycles between successive VSyncs measured by Sync Channel 1 STDI or in 1/256th of a field. The readback from this field is valid if CH1_STDI_DVALID is high.
  • Page 121 Hardware User Guide UG-180 STDI Readback Values Table 45. STDI Readback Values for SD, PR, and HD Standard CHx_BL[13:0] 28.63636 MHz XTAL CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0] 28.63636 MHz XTAL 720p SMPTE 296M 5091 4 to 5 1868 1125i SMPTE 274M 6788 562 to 563 4 to 5 1868...
  • Page 122 UG-180 Hardware User Guide 1200 1000 VGA 72 VGA 75 2000 4000 6000 8000 28.6363MHz SAMPLES IN 8-LINE BLOCK Figure 46. STDI Values for GR Mode (Plot) Note: Although the two points for VGA72 and VGA75 look very close, it is anticipated that the difference in the parameters is sufficient to distinguish between them.
  • Page 123 Hardware User Guide UG-180 As shown in Figure 47, the ADV7611 CP can output the following three primary and one secondary synchronization signals, which are controlled by the output control block in the CP block. Primary: • Horizontal synchronization timing reference output on the HS pin •...
  • Page 124 UG-180 Hardware User Guide CP Synchronization Signals The three primary synchronization signals have certain default positions, depending on the video standard in use. To allow for a glueless interface to downstream ICs, there is the facility to adjust the position of edges on the three primary synchronization signals.
  • Page 125 Hardware User Guide UG-180 PIXEL BUS ..... H BLANK ACTIVE VIDEO ACTIVE VIDEO HS OUTPUT START_HS[9:0] END_HS[9:0] 4 LLC1 Figure 49. HS Timing START_HS[9:0] , Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0] A control to shift the position of the leading edge of the HSync output by the CP core. This register stores a signed value in a twos complement format.
  • Page 126 UG-180 Hardware User Guide END_HS[9:0] , Addr 44 (CP), Address 0x7C[1:0]; Address 0x7D[7:0] A control to shift the position of the trailing edge of the HSync output by the CP core. This register stores a signed value in a twos complement format. HS_END[9:0] is the number of pixel clocks by which the leading edge of the HSync is shifted (for example, 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks toward the active video).
  • Page 127 Hardware User Guide UG-180 Function START_VS[3:0] Description 0x0 (default) Default value. 0x0 to 0x7 The leading edge of the VSync is shifted toward the active video. 0x8 to 0xF The leading edge of the VSync is shifted away from the active video. Table 55.
  • Page 128 UG-180 Hardware User Guide END_VS_EVEN[3:0] , Addr 44 (CP), Address 0x89[3:0] A control to shift the position of the trailing edge of the Vsync output by the CP core. This register stores a signed value in a twos complement format. SEND_VS_EVEN[3:0] is the number of lines by which the trailing edge of the Vsync is shifted (for example, 0x0F corresponds to a shift of 1 line toward the active video, 0x01 corresponds to a shift of 1 line away from the active video).
  • Page 129 Hardware User Guide UG-180 DE_V_END[3:0] , Addr 44 (CP), Address 0x8E[3:0] A control to vary the position of the end of the VBI region. This register stores a signed value represented in a twos complement format. The unit of DE_V_START[9:0] is one line. Function DE_V_END[3:0] Description...
  • Page 130 UG-180 Hardware User Guide Table 58. Controlling the Even Field Section of the FIELD Timing Signal START_FE[3:0] Result Note 0000(default) No move (default) Minimum → 0001 1 HS shift later than default 0011 3 HS shift later than default Maximum → 0111 7 HS shift later than default Minimum ←...
  • Page 131 Hardware User Guide UG-180 FIELD 1 15… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 2 6 2 277… OUTPUT VIDEO HS OUTPUT VS OUTPUT END_VS[3:0] START_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 50. 525i VS Timing Rev.
  • Page 132 UG-180 Hardware User Guide FIELD 1 11… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 323… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 51. 625i VS Timing OUTPUT VIDEO OUTPUT END_VS[3:0] OUTPUT START_VS[3:0]...
  • Page 133 Hardware User Guide UG-180 OUTPUT VIDEO 8… OUTPUT OUTPUT END_VS[3:0] START_VS[3:0] Figure 54. 720p VS Timing FIELD 1 OUTPUT VIDEO 1123 1124 1125 8… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 OUTPUT VIDEO 5 6 3 570… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0]...
  • Page 134 UG-180 Hardware User Guide CP HDMI CONTROLS HDMI_CP_LOCK_THRESHOLD[1:0] , Addr 44 (CP), Address 0xCB[1:0] Locking time of filter used for buffering of timing parameters in HDMI mode. Function HDMI_CP_LOCK_THRESHOLD[1:0] Description 00 (default) Slowest locking time Medium locking time Fastest locking time Fixed step size of 0.5 pixels FREE RUN MODE Free run mode provides the user with a stable clock and predictable data if the input signal cannot be decoded, for example, if input video...
  • Page 135 Hardware User Guide UG-180 CH1_FR_LL[10:0] , Addr 44 (CP), Address 0x8F[2:0]; Address 0x90[7:0] Free run line length in number of crystal clock cycles in one line of video for Sync Channel 1 STDI. This register should only be programmed video standards that are not supported by PRIM_MODE[3:0] and VID_STD[5:0]. Function CH1_FR_LL[10:0] Description...
  • Page 136 UG-180 Hardware User Guide Field line count is the vertical parameter that holds the ideal number of lines per field for a given video standard. It affects the way CP handles the unlocked state. It affects the way CP handles the unlocked state. If CP_LCOUNT_MAX[11:0] is set to 0, the internally used free run line length value is decoded from the current setting of PRIM_MODE[3:0] and VID_STD[5:0].
  • Page 137 Hardware User Guide UG-180 DIS_AUTO_PARAM_BUFF, Addr 44 (CP), Address 0xC9[0] A control to disable the buffering of the timing parameters used for free run in HDMI mode. Function DIS_AUTO_PARAM_BUFF Description 0 (default) Buffer the last measured parameters in HDMI mode used to determine video resolution the part free runs into. Disable the buffering of measured parameters in HDMI mode.
  • Page 138 UG-180 Hardware User Guide Table 60 shows the default colors for component and graphics based video. The values describe the color blue. Setting the CP_DEF_COL_MAN_VAL bit high enables the user to overwrite the default colors with the values given in DEF_COL_CHA[7:0], DEF_COL_CHB[7:0], and DEF_COL_CHC[7:0].
  • Page 139 Hardware User Guide UG-180 CONSUMER ELECTRONICS CONTROL The Consumer Electronics Control (CEC) module features the hardware required to behave as an initiator or a follower as per the specifications for a CEC device. The CEC module contains four main sections: •...
  • Page 140 UG-180 Hardware User Guide CEC TRANSMIT SECTION The transmit section features the hardware required for the CEC module to act as an initiator. The host utilizes this section to transmit directly addressed messages or broadcast messages on the CEC bus. When the host wants to a send message to other CEC devices, it writes the message to the CEC outgoing message registers (refer to Table 61) and the message length register.
  • Page 141 Hardware User Guide UG-180 CEC_TX_READY_ST , IO, Address 0x93[0] (Read Only) Latched status of CEC_TX_READY_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When the CEC TX successfully sends the current message this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_TX_READY_CLR.
  • Page 142 UG-180 Hardware User Guide CEC RECEIVE SECTION The receive section features the hardware required for the CEC module to act as a follower. Once the CEC module is powered up via the CEC_POWER_UP bit the CEC Rx section will immediately begin monitoring the CEC bus for messages with the correct logical address(es).
  • Page 143 Hardware User Guide UG-180 Receive Buffers The ADV7611 features three frame buffers that allow the receiver to receive up to three messages before the host processor needs to read a message out. When three messages have been received, no further message reception is possible until the host reads at least one message.
  • Page 144 UG-180 Hardware User Guide CEC_RX_RDY0_ST , IO, Address 0x93[3] (Read Only) Latched status of CEC_RX_RDY0_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When a message has been received into Buffer 0, this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_RX_RDY0_CLR.
  • Page 145 Hardware User Guide UG-180 CEC_BUF0_RX_FRAME_LENGTH[4:0] , Addr 80 (CEC), Address 0x25[4:0] (Read Only) Function CEC_BUF0_RX_FRAME_LENGTH[4:0] Description xxxxx The total number of bytes (including header byte) that were received into Buffer 0 CEC_CLR_RX_RDY0 , Addr 80 (CEC), Address 0x2C[1] (Self-Clearing) Clear control for CEC_RX_RDY0. Function CEC_CLR_RX_RDY0 Description...
  • Page 146 UG-180 Hardware User Guide Table 64. CEC Incoming Frame Buffer 2 Registers Register Name CEC Map Address Description CEC_BUF2_RX_FRAME_HEADER[7:0] 0x65 Header of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA0[7:0] 0x66 Byte 0 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA1[7:0] 0x67 Byte 1 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA2[7:0] 0x68 Byte 2 of message in Frame Buffer 2...
  • Page 147 Hardware User Guide UG-180 Another message is received. The receiver module checks to see which of the three buffers are available, starting with Buffer 0. In this example, Buffer 0 has been read out already by the host processor and is available so the new message is stored in Receive Buffer 0. At this time the timestamp for Receive Buffer 1 is adjusted to 0b01 to show that it contains the first received message, and a timestamp of 0b10 is assigned to Receive Buffer 0 to show that it contains the second received message.
  • Page 148 UG-180 Hardware User Guide TYPICAL OPERATION FLOW This section describes the algorithm that should be implemented in the host processor controlling the CEC module. Initializing CEC Module Figure 59 shows the flow that can be implemented in the host processor controlling the ADV7611 to initialize the CEC module. START SET CEC_POWER_UP TO 1 ENABLE...
  • Page 149 Hardware User Guide UG-180 Using CEC Module as Initiator Figure 60 shows the algorithm that can be implemented in the host processor controlling the ADV7611 to use the CEC module as an initiator. START WRITE THE OUTGOING CEC COMMAND INTO THE OUTGOING MESSAGE REGISTERS (CEC MAP REG 0x00 TO 0x0F) SET CEC_TX_FRAME_LENGTH...
  • Page 150 UG-180 Hardware User Guide Using CEC Module as Follower Figure 61 shows the algorithm that can be implemented in the host processor controlling the ADV7611 to use the CEC module as a follower. START (WAIT FOR INTERRUPT) CEC_RX_RDY0_ST CEC_RX_RDY1_ST CEC_RX_RDY2_ST = 1? = 1? = 1?
  • Page 151 Hardware User Guide UG-180 LOW POWER CEC MESSAGE MONITORING The ADV7611 can be programmed to monitor the CEC line for messages that contain specific, user-programable opcodes. These are referred to as “WAKE_OPCODEs” as they allow the system to go into a low power or sleep mode and be woken up when an opcode of interest is received, without the host processor having to check each received message.
  • Page 152 UG-180 Hardware User Guide CEC_WAKE_OPCODE4[7:0] , Addr 80 (CEC), Address 0x7C[7:0] CEC_WAKE_OPCODE4 This value can be set to a CEC opcode that requires a response. On receipt of this opcode the Rx generates an interrupt that can be used to alert the system that a CEC opcode of interest has been received and requires a response. Function CEC_WAKE_OPCODE4[7:0] Description...
  • Page 153 Hardware User Guide UG-180 INTERRUPTS INTERRUPT ARCHITECTURE OVERVIEW The ADV7611 interrupt architecture provides four different types of bits, namely • Raw bits • Status bits • Interrupt mask bits • Clear bits Raw bits are defined as being either edge-sensitive or level-sensitive. The following example compares AVI_INFO_RAW and NEW_AVI_INFO_RAW to demonstrate the difference.
  • Page 154 UG-180 Hardware User Guide AVI_INFO_ST , IO, Address 0x61[0] (Read Only) Latched status of AVI_INFO_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Once set, this bit will remain high until the interrupt is cleared via AVI_INFO_CLR. Function AVI_INFO_ST Description...
  • Page 155 Hardware User Guide UG-180 NEW_AVI_INFO_MB2 , IO, Address 0x7C[0] INT2 interrupt mask for new AVI InfoFrame detection interrupt. When set a new AVI InfoFrame detection event will cause NEW_AVI_INFO_ST to be set and an interrupt will be generated on INT2. Function NEW_AVI_INFO_MB2 Description...
  • Page 156 UG-180 Hardware User Guide NEW AVI INFOFRAME DETECTION INTERNAL PULSE FLAG AVI INFOFRAME WITH NEW CONTENT DETECT TIME > 2XTAL PERIODS NEW_AVI_INFO_RAW NEW_AVI_INFO_ST NEW_AVI_INFO_CLR SET TO 1 TIME TAKEN BY THE CPU TO CLEAR NEW_AVI_INFO_ST Figure 64. NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing In this section, all raw bits are classified as being triggered by either level sensitive or edge sensitive events, with the following understanding of the terminology •...
  • Page 157 Hardware User Guide UG-180 Interrupt Duration The interrupt duration can be programmed independently for INT1 and INT2. When an interrupt event occurs, the interrupt pin INT1 or INT2 becomes active with a programmable duration as described below. INTRQ_DUR_SEL[1:0] , IO, Address 0x40[7:6] A control to select the interrupt signal duration for the interrupt signal on INT1.
  • Page 158 UG-180 Hardware User Guide MPU_STIM_INTRQ_MB1 , IO, Address 0x4B[7] INT1 interrupt mask for manual forced interrupt signal. When set the manual forced interrupt will trigger the INT1 interrupt and MPU_STIM_INTRQ_ST will indicate the interrupt status. Function MPU_STIM_INTRQ_MB1 Description 0 (default) Disables manual forced interrupt for INT1 Enables manual forced interrupt for INT1 MPU_STIM_INTRQ_MB2 , IO, Address 0x4A[7]...
  • Page 159 Hardware User Guide UG-180 DESCRIPTION OF INTERRUPT BITS This section lists all the raw bits in the IO map of the ADV7611 by category, and states whether the bit is an edge or level sensitive bit. A basic explanation for each bit is provided in the software manual and/or in the corresponding section of the hardware manual. For certain interrupts that require additional explanations, these are provided in the Additional Explanations section.
  • Page 160 UG-180 Hardware User Guide • DE_REGEN_LCK_RAW • VIDEO_3D_RAW • RI_EXPIRED_A_RAW The following raw bits are all related to HDMI operation and are based on edge sensitive events; it is, therefore, necessary to clear these bits using the corresponding clear bit. •...
  • Page 161 Hardware User Guide UG-180 CP_LOCK, CP_UNLOCK CP_UNLOCK_RAW is programmable as either an edge sensitive bit or a level sensitive bit using the following control. Note that this control also configures whether an interrupt is generated only on the rising edge of CP_UNLOCK_RAW, or on both edges. CP_LOCK_UNLOCK_EDGE_SEL , IO, Address 0x41[5] A control to configure the functionality of the CP_LOCK, CP_UNLOCK interrupts.
  • Page 162 UG-180 Hardware User Guide Group 3 HDMI Interrupts The interrupts listed in Table 68 are valid under the following conditions: • ADV7611 is configured in HMDI mode • TMDS_CLK_A_RAW is set to 1 if Port A is the active HDMI port •...
  • Page 163 Hardware User Guide UG-180 Storing Masked Interrupts STORE_UNMASKED_IRQS , IO, Address 0x40[4] STORE_MASKED_IRQS allows the HDMI status flags for any HDMI interrupt to be triggered regardless of whether the mask bits are set. This bit allows a HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without triggering an interrupt on the interrupt pin.
  • Page 164 UG-180 Hardware User Guide INTERRUPT_STATUS_6 register consists of fields: CP_LOCK_CH1_ST, CP_UNLOCK_CH1_ST, and STDI_DVALID_CH1_ST. CP_LOCK_CH1_ST , IO, Address 0x5C[3] (Read Only) Function CP_LOCK_CH1_ST Description 0 (default) No change. An interrupt has not been generated from this register. Channel 1 CP input has caused the decoder to go from an unlocked state to a locked state. CP_UNLOCK_CH1_ST , IO, Address 0x5C[2] (Read Only) Function CP_UNLOCK_CH1_ST...
  • Page 165 Hardware User Guide UG-180 VS_INFO_ST , IO, Address 0x61[4] (Read Only) Latched status of vendor specific InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via VS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function VS_INFO_ST Description...
  • Page 166 UG-180 Hardware User Guide AV_MUTE_ST , IO, Address 0x66[5] (Read Only) Latched status of AV mute detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via AV_MUTE_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function AV_MUTE_ST Description...
  • Page 167 Hardware User Guide UG-180 Function TMDSPLL_LCK_A_ST Description 0 (default) TMDSPLL_LCK_A_RAW has not changed. An interrupt has not been generated. TMDSPLL_LCK_A_RAW has changed. An interrupt has been generated. TMDS_CLK_A_ST , IO, Address 0x6B[4] (Read Only) Latched status of Port A TMDS clock detection interrupt signal. Once set, this bit will remain high until the interrupt is cleared via TMDS_CLK_A_CLR.
  • Page 168 UG-180 Hardware User Guide HDMI Edg INT Status 1 register consists of fields: NEW_ISRC2_PCKT_ST, NEW_ISRC1_PCKT_ST, NEW_ACP_PCKT_ST, NEW_VS_INFO_ST, NEW_MS_INFO_ST, NEW_SPD_INFO_ST, and NEW_AUDIO_INFO_ST. NEW_ISRC2_PCKT_ST , IO, Address 0x7A[7] (Read Only) Latched status for the new ISRC2 packet interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_ISRC2_PCKT_CLR.
  • Page 169 Hardware User Guide UG-180 NEW_AUDIO_INFO_ST, IO, Address 0x7A[1] (Read Only) Latched status for the new audio InfoFrame interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_AUDIO_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function NEW_AUDIO_INFO_ST Description...
  • Page 170 UG-180 Hardware User Guide PACKET_ERROR_ST , IO, Address 0x7F[2] (Read Only) Latched status for the packet error interrupt. Once set, this bit will remain high until the interrupt is cleared via PACKET_ERROR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function PACKET_ERROR_ST Description...
  • Page 171 Hardware User Guide UG-180 PARITY_ERROR_ST , IO, Address 0x84[4] (Read Only) Latched status of parity error interrupt. Once set, this bit will remain high until the interrupt is cleared via PARITY_ERROR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function PARITY_ERROR_ST Description...
  • Page 172 UG-180 Hardware User Guide SPD_INF_CKS_ERR_ST , IO, Address 0x89[6] (Read Only) Latched status of SPD InfoFrame checksum error interrupt. Once set, this bit will remain high until the interrupt is cleared via SPD_INF_CKS_ERR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function SPD_INF_CKS_ERR_ST Description...
  • Page 173 Hardware User Guide UG-180 HDMI Edg Int Status 5 register consists of the VS_INF_CKS_ERR_ST field. VS_INF_CKS_ERR_ST , IO, Address 0x8E[0] (Read Only) Latched status of MPEG source InfoFrame checksum error interrupt. Once set, this bit will remain high until the interrupt is cleared via MS_INF_CKS_ERR_CLR.
  • Page 174 UG-180 Hardware User Guide REGISTER ACCESS AND SERIAL PORTS DESCRIPTION The ADV7611 has three 2-wire serial (I C compatible) ports: • One main I C port, SDA/SCL, allows a system I C master controller to control and configure the ADV7611 •...
  • Page 175 Hardware User Guide UG-180 write command to IO 0x1B, SAMPLE_ALSB, one part (with VS/FIELD/ALSB left floating) will get Address 0x98 and the second part (with VS/FIELD/ALSB pulled high) will have an address of 0x9A. SAMPLE_ALSB , IO, Address 0x1B[0] When HIGH, VS/FIELD/ALSB pin is sampled to be used as ALSB value for IO map. Function SAMPLE_ALSB Description...
  • Page 176 UG-180 Hardware User Guide DPLL_SLAVE_ADDR[6:0], IO, Address 0xF8[7:1] Programmable I C slave address for DPLL map Function DPLL_SLAVE_ADDR[6:0] Description 0x00 (default) Map not accessible 0xXX DPLL Map Slave address Protocol for Main I C Port The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains high.
  • Page 177 Hardware User Guide UG-180 DDC PORTS An I C port, DDC Port A, allows HDMI hosts to access the internal E-EDID and the HDCP registers. Note that the DDC ports are 5 V tolerant, which simplifies the hardware between the HDMI connector and the ADV7611. C Protocols for Access to the Internal EDID An I C master connected on a DDC port can access the internal EDID using the following protocol:...
  • Page 178 UG-180 Hardware User Guide APPENDIX A PCB LAYOUT RECOMMENDATIONS The ADV7611 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board, in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV7611. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF and a 10 nF capacitor where possible.
  • Page 179 Hardware User Guide UG-180 DIGITAL INPUTS The following digital inputs on the ADV7611 are 3.3 V inputs that are 5.0 V tolerant: • DDCA_SCL • DDCA_SDL Any noise that gets onto the HS and VS inputs trace will add jitter to the system. Therefore, the trace length should be minimized; and digital or other high frequency traces should not be run near it.
  • Page 180 UG-180 Hardware User Guide APPENDIX B RECOMMENDED UNUSED PIN CONFIGURATIONS Table 70. Recommended Configuration of Unused Pins Pin No. Mnemonic Type Recommended Configuration if Not Used Ground Ground. HPA_A/INT2 Miscellaneous digital Float this pin. CVDD Power This pin is always connected to comparator supply voltage (1.8 V). RXA_C- HDMI input Float this pin.
  • Page 181 Hardware User Guide UG-180 Pin No. Mnemonic Type Recommended Configuration if Not Used SCLK/INT2 Miscellaneous digital Float this pin. LRCLK Miscellaneous Float this pin. MCLK/INT2 Miscellaneous Float this pin. DVDD Power This pin is always connected to digital core supply voltage (1.8 V). Miscellaneous digital This pin is always connected to the I C clock line of a control processor.
  • Page 182 UG-180 Hardware User Guide APPENDIX C PIXEL OUTPUT FORMATS Table 71. SDR 4:2:2 and 4:4:4 Output Modes SDR 4:2:2 SDR 4:4:4 OP_FORMAT_SEL[7:0] 0x0A 0x80 0x8A 0x40 8-Bit SDR ITU-R 12-Bit SDR ITU-R 16-Bit SDR ITU-R 24-Bit SDR ITU-R 24-Bit SDR Pixel Output BT.656 Mode 0 BT.656 Mode 2...
  • Page 183 Hardware User Guide UG-180 Table 72. DDR 4:2:2 and 4:4:4 Output Modes DDR 4:2:2 Mode (Clock/2) DDR 4:2:2 Mode (Clock/2) DDR 4:4:4 Mode (Clock/2) 0x20 0x2A 0x60 8-Bit DDR ITU-656 12-Bit DDR ITU-656 24-Bit DDR RGB OP_FORMAT_SEL[7:0] (Clock/2 Output) 4:2:2 Mode 0 (Clock/2 Output) 4:2:2 Mode 2 (Clock/2 Output) Pixel Output...
  • Page 184 By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement.