Operating Modes; Master Mode; Slave Mode - Sino Wealth 8051 Manual

9.7.5 Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes, master mode or slave mode. The configuration and
initialization of the SPI module is made through SPCON (the serial peripheral control register) and SPSTA (the serial peripheral status
register). Once the SPI is configured, the data exchange is made using SPCON, SPSTA and SPDAT (the serial peripheral data
register).
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line
(SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A slave select line ( SS
selection of a SPI slave; SPI slaves that are not selected do not interfere with SPI bus activities.
When the SPI master transmits data to the SPI slave via the MOSI line, the SPI slave responds by sending data to the SPI master via
the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock. Both transmit
shift register and receive shift register uses the same SFR Address, a write operation to SPDAT will write to the transmit shift register,
and a read operation from SPDAT will retrieve the data in receive shift register.
Clock Generator

Master Mode

(1) Mode Enable
A SPI master device initiates all data transfers on a SPI bus. The SPI operates in master mode when the MSTR is set in SPCON
register. Only one master can initiate transmission.
(2) Transmit
When in SPI master mode, writing a byte of data to the SPI data register (SPDAT) will write to the transmit shift buffer. If the transmit
shift register already contains data, the SPI master will generate a WCOL signal to indicate writing too fast. But the data i n transmit
shift register will not be affected, and the transmission continues uninterrupted. Else if the transmit shift register is empty, the SPI
master will immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF flag in SPSTA
register is set to logic '1' at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set
(3) Receive
While the master transfers data to a slave on the MOSI line, the addressed slave simultaneously transfers the contents of its transmit
shift register to the master's receive shift register on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both
a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first or LSB-first into the
master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the
processor by reading SPDAT. If an overrun occurs, RXOV signal will be set to indicate data over-run occurs, and the receive shift
register keep the byte that SPIF was lastly set, also the SPI master will not receive any further data until SPIF was cleared.During
receiving a byte with SPIF cleared,the follwing byte cannot damage the last byte receiving until the last byte has been received.

Slave Mode

(1) Mode Enable
The SPI operates in slave mode when the MSTR is cleared in the SPCON register. Before a data transmission occurs, the slave select
———
) pin of the Slave device must be set to '0'. The SS
(SS
(2) Transmit & Receive
When in SPI slave mode, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the
SCK signal. A bit counter counts SCK edges. When 8 bits have been shifted in the receive shift register and another 8 bits have been
shifted out the transmit shift register, the SPIF flag is set to logic '1'. Data is read from the receive shift register by reading SPDAT. If
interrupts are enabled, an interrupt request is generated when the SPIF flag is set.
To prevent an overflow condition, the SPI slave software must clear the SPIF bit in SPSTA register before another byte enters the
receive shift register. Else a RXOV signal will be set to indicate data over-run occurs, and the receive shift register keep the byte that
SPIF was lastly set, also the SPI slave will not receive any further data until SPIF was cleared.
A SPI slave cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to
SPDAT. Writes to SPDAT are placed in the transmit buffer first. So a SPI slave must complete the write to the SPDAT (transmit shift
register) in one SPI clock before the master starts a new transmission. If the write to SPDAT is late in the first transmission, the SPI
slave will transmit a '0x00' byte in the following transmission. If the write operation occurs during this time, a WCOL signal will be set.
If the transmit shift register already contains data, the SPI slave will generate a WCOL signal to indicate writing too fast. But the data
in transmit shift register will not be affected, and the transmission continues uninterrupted.
8-bit Shift Register
SPI
Master MCU
Full-Duplex Master-Slave Interconnection Diagram
———
pin must remain low until the 1-byte transmission is complete.
MISO MISO
MOSI MOSI
SCK SCK
V
DD
SS SS
V
SS
143
SH79F9461
———
) allows individual
8-bit Shift Register
Slave MCU