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User's guide to BGT60LTR11AIP
60 GHz Radar
2 Main controller
2.2.5
SPI mode sequence
This is the manual mode, main controller is inactive and Reg0/1 are set to all off by main controller. The SPI
sequence just has to switch off quad state inputs. Depending on quad state input QS1, external 9.6 MHz clock is
enabled (QS1="10") or not (QS1="11").
Table 11
SPI mode sequence in detail
Command
1
write Reg1 0x0000
2
end
Optionally, it is also possible to configure the registers and activate the pulsed mode or CW mode afterwards.
This can be done by setting start_pm (Reg15[14]) to "1". This enters pulsed mode if start_cw=0 (Reg15[12]), CW
mode otherwise.
If external clock is enabled (QS1="10") it can be switched off with the same SPI access by setting bit clk_ext_dis
(Reg15[13]). When the clock is switched off, 16-32 further clocks are delivered to allow the external component
to go to a sleep state.
2.2.6
Detector
When RF blocks are switched on, the detector can be activated. It takes another 50 ms after enabling of
detector for settling of baseband. During this time the outputs TDet and PDet are kept in inactive state.
2.3
Overview dynamic control signals
Table 12
Overview dynamic control signals
vcobuf_en, vco_en
pll_clk_gate_en, pll_active toggling
pll_open_loop
pll_en
mpa_en
rxbuf_en, txbuf_en
mixi_en, mixq_en
lna_en
div_bias_en
qs_rd_en
bb_dig_det_en
bb_boost_dis
bb_clk_chop_en
bb_strup_hp
bb_amp_en
(table continues...)
Application Note
Autonomous pulsed mode
toggling
0
1
toggling
toggling
toggling
toggling
toggling
0
1
0
1
0
1
Description
Reset bit qs_rd_en
Autonomous CW mode
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
16
SPI mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V1.5
2022-08-01
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