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Chapter 16
16.4.6 Continuous mode (slave mode, transmission/reception
CBnTX
SCKBn
SOBn
SIBn
INTCBnT
INTCBnR
CBnTSF
CBnSCE
Shift register
SO latch
CBnRX
(1)
(2)
(3)
(4)
442
(8) Overrun error processing is performed after checking that the
CBnOVE bit = 1 in the INTCBnR interrupt servicing.
(9) Clear CBnOVE bit to 0.
(10)Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
stop the operation CSIBn (end of reception).
mode)
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.3 (2)
CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits
(CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
55H
0
1
0
1
0
1
1
0
0
1
(5)
(6)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
User's Manual U18743EE1V2UM00
AAH
1
0
1
1
0
1
0
1
0
0
1
0
0
1
CCH
CCH
(7)
Clocked Serial Interface (CSIB)
1
0
1
0
0
1
1
0
96H
96H
(7)
(8)
00H
00H
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