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IC805 VHIHY57V16D-1: DRAM (HY57V16D)
PIN
Terminal Name
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA
Bank Address
A0~A10
Address
RAS,CAS,WE
ROW Address Strobe, Column
Address Strobe, Write Enable
LDQM,UDQM
Data Input/Output Mask
DQ0~DQ15
Data Input/Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
NC
No Connection
IC805 VHIHY57V16D-1: DRAM (HY57V16D)
the system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh.
Command input enable or mask except CLK, CKE and DQM.
Select either one of bank during both RAS and CAS activity.
Row address:RA0~RA10, Column Address:CA0~CA7
Auto-precharge flag:A10
RAS, CAS and WE define the operation. Refer function truth table for details.
DQM control output buffer in read mode and mask input data in write mode
Multiplexed data input/output pin.
Power supply for internal circuit and input buffer.
Power supply for DQ.
No connection
1
V
DD
DQ0
2
DQ1
3
V
4
SSQ
DQ2
5
DQ3
6
V
DDQ
7
DQ4
8
DQ5
9
V
SSQ
10
11
DQ6
12
DQ7
13
50pin TSOP ll
VDDQ
400mil x 825mil
14
LDQM
0.8mm pin pitch
15
/WE
16
/CAS
17
/RAS
18
/CS
19
A11
20
A10
21
A0
22
A1
23
A2
24
A3
25
V
DD
Self Refresh Counter
Refresh
Refresh
Interval Timer
Counter
Address[0:10]
CLK
Address
Precharge
CKE
Register
Row Active
BA(A11)
Column Active
CS
RAS
Burst Length
Counter
CAS
WE
UDQM
LDQM
Mode Register
Figure 10 BLOCK DIAGRAM OF IC
Function
V
SS
50
DQ15
49
DQ14
48
VSSQ
47
DQ13
46
DQ12
45
VDDQ
44
DQ11
43
DQ10
42
VSSQ
41
DQ9
40
DQ8
39
VDDQ
38
37
NC
36
UDQM
35
CLK
34
CKE
NC
33
32
A9
31
A8
A7
30
A6
29
A5
28
A4
27
V
SS
26
512Kx16
Bank 0
Sense AMP & I/O gates
Column Decoder
Column Addr.
Latch & Counter
Overflow
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 1
Test Mode
I/O Control
8 – 11
XL-MP80H/MP80E
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
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