CIRCUIT DESECRIPTION
Transmit PLL Loop
The divide ratio is increased by 91 during transmit opera-
tions. This causes the TX VCO
frequency to be locked at a
frequency
455kHz
higher
than the RX
VCO
frequency
which prevents internal mixing. When an error occurs that
is greater than the correction voltage limits an unlock signal
is generated by !C1. This signal controls the conduction of
Q1 : 2SC2458(Y) which controls Q2 : 2SA1048(Y) to stop
transmissions.
Q2
interrupts
the bias of the TX
driver
stage..
EEEEEEDEERNEAR
N13 -° N11
N44
N2
Fig. 7
MC145151P Block diagram (PLL unit IC1)