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(4) DC-DC converter
At the power on, Q5 turns ON
by the base current
through R50. The collector current of Q5 generates the
voltage
on
the winding
N1
and
N2.
The
positive
voltage on the terminal 7 for the terminal 6 (GND)
increases the collector current of Q5 through R55 and
C23. When the transformer gets satulated, the Q5 turns
OFF.
After some
period, the level of the base of Q5
goes up by the charge current through
R50, and Q5
turns ON again.
The circuit repeats this cycle. Thus the voltage is gener-
ated on N1, N2 and N3, 034 and 035 rectifies the
voltage of N2. When
Vcc exceeds the specified zener
voltage, the current flows through ZD2 and D33 and
turns Q4 ON and Q5 OFF to regulate Vcc and VLL to
the specified voltage.
Q5___collector
be—teye
in3
+20V
min
30kHz.
approx.
+10V
approx,
GND
—
Fig. 13
Display
The uPD75208 has a built-in display controller which reads
out the contents of the display memory
and automatically
generates digit and segment signals and a high voltage out-
put
buffer
which
can
directly drive fluorescent
display.
The
output
of timing signals and
segment
signals are as
follows. (Fig. 14)
—12—
————
Osplay
cycte
__
(ae
e
lany [aot eee
°
fel
ae gy
Seen
| es ee
J
ee
-
|
|
AoA
AH
o
eres
i
ee
Se
|
reg:
fee
rere
on ee a
eae
Ceres icy (ee eee
| | Key
scan
timng
Oe TE Gb GS GE? GO CAD ED CED CD GD GE Gd GD
Fig. 14
ot
4 4 4
~~
@
a
US
ieee,
| ny
da
oP
Name of Segment
Fig. 15
Key scan
KT1
~ KT7 are provided as inputs for numeric
keys and
function keys from CPU
(IC2), When
a key is depressed.
KTn
(KT1 ~
KT7)
pulse appears on Km
(KO ~ K3) line
through
the keyboard.
Then
CPU
catches
the pulse and
decides
which
order to perform
by matching it up with
"the signal CPU discharged. Also, KTn signal is used for mode
control lock.
in case of depressing[1]Key
kt
J
L011)
K3-——_——"L"
KT1~ eaamelia
Selteas K3
eo eee
GhDeed
eee ee
Fig. 16
i
a a N
c e a A
h s
et
Be
te a N
odT B
Ain rosi
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