HP 5308A Operating And Service Manual page 30

Model 5308A
Theory of Operation
generated on the TB OUT line that clocks U17B by
disabling U12A. The next LOG pulse, which follows
immediately thereafter, passes through Q7, U24A, UTE
and D, and U20B and closes the AGFF. The Low output
of U17A(5) disables USB and ends the measurement.
9H-4-30. Period B Mode
9H-4-31. Ina single period measurement, the internal
clock signal is counted in the mainframe's counter
assembly during one period of the Channel B signal.
Before the clock signal is counted, itis first divided in the
Time Base Decades (mainframe). The division is a
function of the front-panel Time Base switch and serves
to vary the measurement's resolution. Refer to Period B
Mode Flow Diagram, Figure 9H-4-4.
9H-4-32. Atthe beginning of the measured period, the
output of U4C goes Low and clocks the AGFF, U17A, via
U7C, U7D, and U20B. The resultant High on the Q out-
put enables the TB OUT signal to pass through the Aux-
iliary Main Gate, and into the High Speed Decade. The
signal then travels to the mainframe's counter on the F1
line.
9H-4-33. When the AGFF was set at the beginning of
the period, the Q output went Low and caused U12B and
D to clock U17B. This occurs almost instantly after the
AGFF sets and lags only by the propagation delays of
the gates themselves. Once clocked, U17B places a Low
on the D input of U17A. Thus, the AGFF is ready to close
the Auxiliary Main Gate at the endofthe period, i.e., the
next negative-going output of U4C.
9H-4-34, Period Average B Mode
9H-4-35. In a period average measurement, the
counter samples a group of periods and displays the
average value. The number of periods selected is always
in powers of ten (102, 10°, 104, etc.) and is a function of the
TIME BASE switch. For the following description, refer
to Period Average B Flow Diagram, Figure 9H-4-5.
9H-4-36. At the beginning of the measurement, the
"time zero" LOG pulse clocks the AGFF(U17A) via UTE,
U7D, and U20B. This opens the Auxiliary Main Gate at
U8B and allows the 10 MHz clock signal to enter the
High Speed Decade and the mainframe's counter assem-
bly. At the same time, the Channel B signalis sent to the
mainframe's Time Base Decade through U21E and D.
9H-4-37. In addition to opening the Auxiliary Main
Gate, the High level at U17A(5) also enables U12A. This
places a low on the clock input of U17B. Once the main-
frame's Time Base Decade accumulates 10N periods,
the TB OUT line goes Low, which disables U12A and
U12D and clocks U17B. This places a Low on the D input
of U17A, allowing the next LOG pulse (immediately
following) to clock U17A and close the Auxiliary Main
Gate.
9H AA
9H-4-38. Totalize A AA B Mode
9H-4-39. This mode allows Channel A pulses to
totalize for the time between Channel B pulses. The
counter can be used as a stop watch when in the CHK
function by using the O/C switch to manually start and
stop the accumulation of clock pulses. Both modes are
explained in the following paragraphs. Refer to the
Totalize A A A B Mode Flow Diagram, Figure 9H-4-6.
9H-4-40. TOTALIZE "A" BETWEEN "B" PULSES.
Assume that Channel B is set to trigger on the positive
slope. See Totalize A AA B Flow Diagram, Figure 9H-
4-6. The first positive-going Channel B pulse forces
U7C(4) Low and clocks U17A through U7D and U20B.
9H-4-41. The Channel A signal passes through U21C
and D and enters the mainframe's Time Base Decades.
The signal is divided by a factor determined by the set-
ting of the TIME BASE switch. As the divided signal
returns on the TB OUT line, it passes through Q8, USB
and D, USB and D, and the High Speed Decade and
returns to the mainframe on the Fl line. Immediately
after the AGFF was set, the Low output of Q disabled
U12B and U12D. This caused U17B to clock a Low level
onto its Q output. Upon arrival of the next positive-going
Channel B pulse, the AGFF is clocked in the same
manner as before. This time, however, the flip-flop
transfers a Low level to the Q output, which disables
U8B and terminates the measurement. No further
measurements can be taken until the RESET button is
pushed. This releases the INHIBIT signal from the reset
inputs of UL7A and B.
9H-4-42. TOTALIZE WITH O/C SWITCH. This mode
operates in the same manner as that described above,
except that the Channel B pulses are manually produced
with the O/C switch. Pushing the O/C switch grounds
U16A(1), causing a High level at pin 2. The two cross-
coupled inverters prevent contact bounce of the O/C
switch from disrupting the other circuits. The differen-
tiator circuit of C16 and R33 produces a positive spike
from the voltage level change at U16 pin 2. This spike
passes through U20A to pin 4 of U20B. Since this is an
exclusive OR gate, the two positive inputs force the out-
put to a Low state. On the trailing edge of the spike, the
output of U20B returns High and clocks the AGFF.
9H-4-43, Totalize A LU B
9H-4-44, This mode operates in the same manner as
does the Totalize A A A B Mode shown in Figure 9H-4-6
except the counter totalizes Channel A pulses while
Channel B is held at a specified level. The difference
between the modes results from a static level change at
U11A(13). In this mode, the level is Low. Input trigger-
ing is related to the slope switch setting as follows:
Channel 8 Stope Switch _/7 Channel B Slope Switch Y
Start ge Start, Stop