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TRC-70
CIRCUIT DESCRIPTION
Control Unit
¢
Control unit configuration
The main LSI chips in-the control unit include CPU :
IC302, ROM : 1C310, EEPROM : 1C311, and extended
YO IC : IC300.
The CPU reads the program from the ROM, reads/
writes memory channel data to EEPROM, and inputs
and outputs signals from the CPU ports or extended I/
O IC ports.
The address signal (8 low-order bits) required for the
CPU to access the ROM, EEPROM, and extended 1/0
iC is multiplexed with other data and output to the bus
line.
The address
is maintained for the necessary
period of time by latching 1C303.
The chip select (CS) signal, which selects a the
desired device (ROM, EEPROM,
etc.}, is supplied to
each device by decoding the address signal by C304 :
10
*
Bus operation
The ROM (IC310), EEPROM (1C311), and extended
I/O IC (IC300) are connected to the CPU (IC302) via the
bus line. When the CPU accesses these ICs (iC310,
1C311, and 1C300), the address signals (A13 to A15)
output from the CPU are decoded by 1C304, and the IC
is specified by the CS signal.
1C310 (ROM) uses the
CPU address signal A15 as a CS signal.
Table 2 is a truth table for IC304.
This bus is a multiplexed bus onto which an address
code and data are output alternately. Therefore, when
the CPU accesses one of the ICs, the necessary ad-
dress signal is latched by IC303.
This latch uses the positive pulse applied to the ALE
pin, after the CPU outputs an address.
TC74HC138AF.
INPUT
OUTPUT
AlB|cC1¥o!¥1 1 Y2! 3]
Ya | Ys | Ye | Y7
oj;/o;o;otl1}7}1/111
71
41
o;/oj1);1/o0;1]/14)1)15111
ofi};olr}1}o0%r1f}4]144
41
olfi}airir}+riorprtr1)
14d
ass}
10304
7/o0/}o};1}1]71]1)/o0 47141 41
(decoder)
1
0
1
|
|
1
1
1
0
4
1
TC74HCI3Z8AF
7/1704]
47477
$7 $1) 041
1/1)
a7r)1]a]r74faqgia]o
ABA5
1c 302
TAble 2 Truth table for IC304 : TC74HC138AF
(CPU)
A0-7
IC303
(Latch)
sPD7BCIOAG-36
TC74HCS73AF
N—p CS
00~7
Ke
IC3IO
A0-I3
(ROM)
27CI28-20
cs
<<
|s{
is)
IC3Il
2
ST Taoctol|
(EEPROM)
w
m
g
MSM28C16 A-20RS
[cs
kK
Ic300
AO-2
(Extended {/0)
CXxDIO95Q
Fig. 5 Control unit block diagram
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