Kenwood TM-731A Service Manual page 14

TM-731A/E
CIRCUIT DESCRIPTION
* PLL Data Output
Pins P6O (CP (PLL Clock}), P61 (DP (DLL Data)), P62 (EP1
(430 MHz PLL Enable)), and P63 (EP2 (144 MHz PLL Enable))
of the microprocessor supply the PLL data.
Fig. 19 indicates the bit structure of the data.
Fig. 20 indicates the timing of the data transfer.
Shift register
Swallow
counter division 2042 '|22[23}e4|23 24
ratio A \
|
Main counter —_-—_—_| olotlozlos'
division ratio N 2 E Ee le
Output port
and reference
MSB
24 [2s 26|27 28/29
frequency
selection
Fig. 19 PLL Data Structure
14
144 MHz Band
The 21 data bits are obtained as follows:
(PEELE Reese ere
1
1
|
(
|
1
d
(
Hi
I
i
AT TTT
Fig. 20 PLL Data Transfer Timing
430 MHz Band
The 21 data bits aré derived as follows:
1. Division data A and'N (17 bits) 4. Division data A and N (17 bits)
F (displayed value
— 10.7 MHz in RX)
F (displayed value — 30.825 MHz in RX}
= {(NxX128)+A}xX12.8 MHz+ref
= {(Nx 128)+A}
x 12.8 MHz+ref
N: 10-bit binary value; division ratio of main counter
N: 10-bit binary value; division ratio of main counter
A: 7-bit binary value; division ratio of swallow counter
A: 7-bit binary value; division ratio of swallow counter
. Reference. frequency (ref) selection (2 bits)
2. Reference frequency (ref) selection (2 bits)
Phase reference
Phase reference
Data Data
fraquency
frequency
Di
02
D1
02
L L
5 kHz
With 5 kHz, 10 kHz, 20 kHz,
L L
5 kHz With 5 kHz,
10 kHz, 20 kHz,
or 25 kHz steps
or 25 kHz steps
H L
6.25 kHz
With 12.5 kHz steps
H
L 6.25 kHz
With 12.5 kHz steps
3. Switch selection (2 bits)
3. Switch selection (2 bits)
Data
Output port
Data
Output port
D3
D4 sw sw2
D3 D4
swt sw2
H H H H
At RX
With ACC OFF
H H H
At RX
L H
L H
At TX
With ACC OFF L
H L H
At TX
H t H L At RX With ACC ON
L H L H At TX With ACC ON