Table of Contents
Advertisement
The C counter instructions have two fields plus some bits which are available for expanding the
size of the C counter:
, . . . . - - - - - - - - - - - - - - - o p e r a t i o n code
r----------
available for expansion
- - - - - w h i c h counter positions
0 0 0
18
10
9 8
7
1
DETAILED BLOCK DIAGRAM
The detailed block diagram shows many more data paths of the data communications processor
includingdata paths for the memory unit, the buffer selector, and the controller selector.
In
general, data flows from one or more registers to the lower data bus, through the Y register to
the arithmetic unit, to the Z drivers, and then to one or more of the registers connected to the
upper data bus. As illustrated below, data may also flow from the memory to the arithmetic unit
at the same time that data is coming from the Y register.
Data coming from a working register, going to a transmit data line under program control, flows
from the working register to the lower data bus into the Y register. From the Y register the data
flows through the arithmetic unit and the Z drivers onto the upper data bus, where it is then
distributed to the buffer selector.
The buffer selector then routes the data to the proper output
channel.
Data being received from a specified remote terminal is temporarily stored in a receive channel
buffer.
The buffer selector then routes the data from the receive channel through the receive
data lines to the lower data bus where it is then sent to the Y register. From the Y register the
data is sent through the arithmetic unit to the Z drivers where it is then distributed to the proper
working register under program control.
The flow of data to and from the controller selector follows the same paths as for the buffer
selector, with the exception that data going to a high speed peripheral comes from memory and
data coming from a high speed peripheral is put into memory without first going through a
working register.
Data flows to and from the controller selector under automatic control of the
DATANET-30 circuitry.
The register transfer instructions, a major class of instructions, permit any combination of up to
six (specific) registers to be combined in the Y register, to be manipulated in some selected
manner, and then have the result put in any combination of up to four (specific) registers. Further
details of the register transfer instructions are given in the instruction repertoire description
but note that the general data flow pattern still applies: data flows to the Y register, through the
arithmetic unit, to the Z drivers, and then to the destination(s).
-52-
Advertisement
Table of Contents
