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PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7
architecture
Serial Communications Block (SCB)
uart_rx
Active
power mode
A -> DS
2
1
Setup IOSS/GPIO
Figure 26-19. UART Start skip and wakeup from Deep Sleep
Note that the above process works only for lower baud rates. The Deep Sleep to Active power mode transition
and CPU enabling the UART receive functionality should take less than 1-bit period to ensure that the UART
receiver is active in time to detect the '0' to '1' transition.
In step 4 of the above process, the firmware takes some time to finish the wakeup interrupt routine and enable
the UART receive functionality before the block can detect the input rising edge on the UART RX line.
If the above steps cannot be completed in less than 1 bit time, first send a "dummy" byte to the device to wake it
up before sending real UART data. In this case, the SKIP_START bit can be left as 0. For more information on how
to perform this in firmware, visit the UART section of the PDL.
Break detection
Break detection is supported in the standard UART mode. This functionality detects when UART RX line is low (0)
for more than UART_RX_CTRL.BREAK_WIDTH bit periods. The break width should be larger than the maximum
number of low (0) bit periods in a regular data transfer, plus an additional 1-bit period. The additional 1-bit period
is a minimum requirement and preferably should be larger. The additional bit periods account for clock
inaccuracies between transmitter and receiver.
For example, for an 8-bit data frame with parity support, the maximum number of low (0) bit periods is 10 (START
bit, 8 '0' data frame bits, and one '0' parity bit). Therefore, the break width should be larger than 10 + 1 = 11
(UART_RX_CTRL.BREAK_WIDTH can be set to 11).
Note that the break detection applies only to receive functionality. A UART transmitter can generate a break by
temporarily increasing TX_CTRL.DATA_WIDTH and transmitting an all zeroes data frame. A break is used by the
transmitter to signal a special condition to the receiver. This condition may result in a reset, shut down, or
initialization sequence at the receiver.
Break detection is part of the LIN protocol. When a break is detected, the INTR_RX.BREAK_DETECT interrupt
cause is set to '1'.
Figure 26-20
and a break width of 12-bit periods).
Regular frame
uart_rx
STOP
Break frame (12 low/0-bit periods)
uart_rx
STOP
Figure 26-20. UART – Regular frame and break frame
Reference manual
IDLE/STOP
START
Deep Sleep
UART not operational
3
illustrates a regular data frame and break frame (8-bit data frame, parity support,
D
D
D
D
START
st
nd
rd
th
1
bit 2
bit 3
bit 4
bit 5
START
DS -> A
4
CPU enables Rx functionality
IOSS/GPIO wake up interrupt
D
D
D
D
th
th
th
th
th
bit 6
bit
7
bit
8
bit 9
356
D
START
1
st
bit
Active
5
UART RX synchronizes
6
P
STOP
bit
STOP
UART Rx
synchronizes
002-18176 Rev. *K
2023-07-26
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