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L M K 0 4 8 1 6
Clock Outputs Tab
The Clock Outputs tab allows the user to control the output channel blocks, including:
Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2)
Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks)
Digital Delay value and Half Step
Clock Divide value
Analog Delay value and Delay bypass/enable (per output)
Clock Output format (per output)
This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total PLL2
N divider value is the product of the VCO Divider value and the PLL N Prescaler and N Counter
values (shown in the PLL2 tab), and is given by:
PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter
E V A L U A T I O N
B O A R D
Figure 9: Clock Outputs tab
27
O P E R A T I N G
I N S T R U C T I O N S
SNLU107
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