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4.2 Transimpedance Amplifier Circuit
The transimpedance amplifier (TIA) circuit is located on the lower half of the OPA928EVM. This configuration
functions as a front end to convert femtoampere-level input currents into voltage outputs. The input path consists
of BNC connector (J5) and 0-Ω series resistor (R4) connected to the inverting input of the OPA928 (U2). The
inverting input can be accessed directly through pin sockets P1 and P2.
Bias
P3
R9
100 k
¢
J5
R4
0
¤
R6
0
£
SH3
SH5
SH1
SH4
SH6
SH2
The noninverting input of the TIA is tied directly to the analog ground of the TIA circuit. The guard copper
surrounding the TIA is grounded as well, which provides very good leakage performance because the offset
voltage of a guard driver is not present between the input and guard traces. When using grounded guard traces
in a PCB layout, make sure to keep power and digital grounds separate from the guard and prevent ground
loops from occurring.
The default feedback path for the TIA consists of a 10-GΩ surface mount resistor (RF) in a resistive
transimpedance configuration. The feedback loop can be configured through the pin sockets, or by installing
and removing jumpers across certain jumper blocks.
and other functions of the TIA circuit.
The sensitive input traces and feedback components of the TIA are guarded from leakage currents using the
techniques described in
Section
on the bottom of the PCB and are fully enclosed by a grounded RF shield to prevent noise and EMI from
coupling into the signal path. For configurability, sensitive input and feedback nodes are also exposed on the top
layer at P1, P2, JP2a, and JP3a. The top-side shield encloses these nodes and is sized to accommodate large
through-hole components inserted between the TIA pin sockets. If using through-hole components enclosed
within the top-side shield, make sure that the component and leads do not come into contact with the shield.
The TIA circuit features two additional functions described in
T-switch that discharges the feedback path to reset measurements in the integrator configuration. The second
function uses the OPA928 internal guard buffer in a guarded diode limiter to protect the TIA from overcurrent
events. For a detailed description and configuration of these functions, see
SBOU282A – DECEMBER 2022 – REVISED MARCH 2023
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TP7
TP11
C8
1 pF
JP2a
RF
10 G
CF
100 pF
JP3a
P1
P2
V+
C1
100 nF
–
OPA928
+
Guard
C2
D1
100 nF
V–
3.6 V
SH7
K2
DGND
Figure 4-2. TIA Circuit Schematic (Simplified)
Section 4.2.1
2.1. The amplifier, input traces, and SMD feedback components are placed
Copyright © 2023 Texas Instruments Incorporated
J8
1 2 3
V+
V–
JP2b
P6
JP3b
Rgb
DNP
P4
P5
Rga
0
§
TP8
TP9
2
R13
1
0
¦
JP4
C9
R5
100 pF
10 k
¨
R8
R7
750
750
2
1
R11
R12
100 k
100 k
©
J7
describes how to configure the feedback path
Section
4.2.2. The first function is a low-leakage
Section
EVM Circuit Description
Rgnd
0
¥
TIA
Hi-Z
GND
GND
P7
J9
2
1
3
Bias
TP10
J6
Riso2
50
¡
C5
DNP
R10
0
K1
TIA
DGND
GND
DGND
4.2.2.
OPA928 Evaluation Module
7
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