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Enclustra Mercury KX1 User Manual

Fpga module
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Mercury KX1 FPGA Module
Purpose
The purpose of this document is to present the characteristics of Mercury KX1 FPGA module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury KX1 FPGA module.
Summary
This document first gives an overview of the Mercury KX1 FPGA module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-KX1
Reference
D-0000-411-002
Name
DIUN
GLAC
DIUN
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury KX1 FPGA Module
Version
07
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
16.02.2021
Date
10.06.2016
24.06.2016
16.02.2021

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Summary of Contents for Enclustra Mercury KX1

  • Page 1 User Manual Purpose The purpose of this document is to present the characteristics of Mercury KX1 FPGA module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury KX1 FPGA module. Summary This document first gives an overview of the Mercury KX1 FPGA module followed by a detailed description of its features and configuration options.
  • Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.

  • Page 3: Table Of Contents

    Table of Contents Overview General ........... 1.1.1 Introduction .
  • Page 4 Signal Description ..........41 Enclustra Module Configuration Tool ........41 I2C Communication Overview .

  • Page 5: Overview

    Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty product return.

  • Page 6: Electrostatic Discharge

    Warning! It is possible to mount the Mercury KX1 FPGA module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury KX1 FPGA module.

  • Page 7: Deliverables

    1.4.1 Reference Design The Mercury KX1 FPGA module reference design features an example configuration for the Kintex-7 FPGA device, together with an example top level HDL file for the user logic. A number of software applications are available for the reference design, that show how to initialize the peripheral controllers and how to access the external devices.

  • Page 8: Mercury+ St1 Base Board

    Please note that the available features depend on the equipped Mercury module type. Xilinx Tool Support The FPGA devices equipped on the Mercury KX1 FPGA module are supported by the Vivado HL WebPACK Edition or by the Vivado HL Design Edition software, depending on the device’s density. Table 1 presents the correspondence between devices and tools.

  • Page 9: Module Description

    Figure 1: Hardware Block Diagram The main component of the Mercury KX1 FPGA module is the Xilinx Kintex-7 FPGA device. Most of its I/O pins are connected to the Mercury module connectors, making 158 regular user I/Os available to the user.

  • Page 10: Module Configuration And Product Codes

    Figure 2: Product Code Fields Please note that for the first revision modules or early access modules, the product code may not respect entirely this naming convention. Please contact Enclustra for details on this aspect. Article Numbers and Article Codes Every module is uniquely labeled, showing the article number and serial number.

  • Page 11: Module Label

    The correspondence between article number and article code is shown in Table 3. The article code repre- sents the product code, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury KX1 FPGA Module Known Issues and Changes document [6].

  • Page 12: Article Numbers And Article Codes

    Article Number Article Code EN100029 ME-KX1-160-1C-D10-R2 EN100004 ME-KX1-325-2I-D11-P-R2 EN100089 ME-KX1-325-1C-D10-R2 EN100590 ME-KX1-410-2I-D11-P-R2 EN100871 ME-KX1-410-2C-D11-P-R2 EN101015 ME-KX1-160-1C-D10-R3 EN101421 ME-KX1-160-1C-D10-R3 EN101017 ME-KX1-325-2I-D11-P-R3 EN101515 ME-KX1-325-2C-D10-P-R3 EN101018 ME-KX1-410-2I-D11-P-R3 EN101422 ME-KX1-325-1C-D10-R4 EN101016 ME-KX1-325-1C-D10-R4 EN101519 ME-KX1-160-1C-D10-R4.1 EN101520 ME-KX1-325-2I-D11-P-R4.1 EN101424 ME-KX1-410-2I-D11-P-R4.1 EN101816 ME-KX1-160-1C-D10-R5 EN101921 ME-KX1-325-2C-D10-P-R5 EN101818 ME-KX1-325-2I-D11-P-R5 EN101819 ME-KX1-410-2I-D11-P-R5 Table 3: Article Numbers and Article Codes...

  • Page 13: Top And Bottom Views

    Top and Bottom Views 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. D-0000-411-002 13 / 50 Version 07, 16.02.2021...

  • Page 14: Top And Bottom Assembly Drawings

    Top and Bottom Assembly Drawings 2.5.1 Top Assembly Drawing Figure 6: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 7: Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document.

  • Page 15: Module Footprint

    Figure 8: Module Footprint - Top View Warning! It is possible to mount the Mercury KX1 FPGA module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury KX1 FPGA module.

  • Page 16: Mechanical Data

    Mechanical Data Table 4 describes the mechanical characteristics of the Mercury KX1 FPGA module. A 3D model (PDF) and a STEP 3D model are available [8], [9]. Symbol Value Size 54 mm Component height top 4.0 mm Component height bottom 1.45 mm...

  • Page 17: User I/O

    User I/O 2.9.1 Pinout Information on the Mercury KX1 FPGA module pinout can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only.

  • Page 18: Differential I/Os

    The information regarding the length of the signal lines from the FPGA device to the module connector is available in Mercury KX1 FPGA Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application.

  • Page 19: Vref Usage

    FPGA device, as well as other devices on the Mercury KX1 FPGA module. Do not leave a VREF pin floating when the used I/O standard requires a reference voltage, as this may damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module. 2.9.5...
  • Page 20 Use only VCC_IO voltages compliant with the equipped FPGA device; any other voltages may damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module. Do not leave a VCC_IO pin floating, as this may damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module.

  • Page 21: Signal Terminations

    Internal differential termination is available only for certain VCCO voltages; please refer to Xilinx AR# 43989 for details. Single-Ended Outputs There are no series termination resistors on the Mercury KX1 FPGA module for single-ended outputs. If required, series termination resistors may be equipped on the base board (close to the module pins). 2.9.7 Analog Inputs The Kintex-7 FPGA devices provide a dual 12-bit ADC.

  • Page 22: Power Generation Overview

    Power Generation Overview The Mercury KX1 FPGA module uses a 5 - 15 V DC power input for generating the on-board supply voltages (1.0 V, 1.2 V, 1.35 V/1.5 V, 1.8 V, 2.0 V, 2.5 V and 3.3 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector.

  • Page 23: Power

    DC/DC converters for 1.0 V, 1.2 V, 1.35/1.5 V, 1.8 V, and 2.5 V. The 3.3 V supply is always active. The PWR_EN input is pulled to VCC_3V3 on the Mercury KX1 FPGA module with a 10 k resistor. The PWR_GOOD signal is pulled to VCC_3V3 on the Mercury KX1 FPGA module with a 10 k resistor.

  • Page 24: Voltage Supply Inputs

    High performance devices like the Xilinx Kintex-7 FPGA need cooling in most applications; always make sure the FPGA is adequately cooled. Table 15 lists the heat sink and thermal pad part numbers that are compatible with the Mercury KX1 FPGA module.

  • Page 25: Voltage Monitoring

    2.11.7 Voltage Monitoring Several pins on the module connector on the Mercury KX1 FPGA module are marked as VMON. These are voltage monitoring outputs that are used in the production test for measuring some of the on-board volt- ages.

  • Page 26: Reset

    2.14 LEDs Four LEDs are available on the Mercury KX1 FPGA module and they are connected to the FPGA logic. An- other LED is connected to the Cypress FX3 USB 3.0 controller user pin for easy status signaling. Table 19 shows the pin locations of the FPGA LEDs.

  • Page 27: Ddr3 Sdram

    2.15 DDR3 SDRAM There are two independent DDR3 memory channels on the Mercury KX1 FPGA module: DDR3-A is 8 bits wide, while DDR3-B is 32 bits wide. Five identical 8-bit memory chips are used to build the entire memory sub-system.

  • Page 28: Ddr3 Sdram Type

    2.15.2 Signal Description Please refer to the Mercury KX1 FPGA Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR3 SDRAM connections. 2.15.3 Termination Warning! No external termination is implemented for the data signals on the Mercury KX1 FPGA module. There- fore, it is strongly recommended to enable the on-die termination (ODT) feature of the DDR3 SDRAM device.

  • Page 29: Ddr3 Low Voltage Operation

    Table 22: QSPI Flash Types Warning! Other flash memory devices may be equipped in future revisions of the Mercury KX1 FPGA module. Please check the user manual regularly for updates. Any parts with different speeds and temperature ranges that fulfill the requirements for the module variant may be used.

  • Page 30: Signal Description

    FPGA and the flash device. 2.17 Dual Gigabit Ethernet Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury KX1 FPGA module, connected to the FPGA via RGMII interfaces. 2.17.1 Ethernet PHY Type Table 24 describes the equipped Ethernet PHY device type on the Mercury KX1 FPGA module.

  • Page 31: Dual Gigabit Ethernet

    Depending on the used IP core, configuration of the RGMII delays in the Ethernet PHYs may be required to achieve proper timing. For details on the RGMII delays, please refer to the PHY datasheet. An example of PHY configuration is shown in the lwIP application provided in the Mercury KX1 FPGA module reference design [2].

  • Page 32: Cypress Fx3 Usb 3.0 Controller

    2.18 Cypress FX3 USB 3.0 Controller The Mercury KX1 FPGA module features a USB 3.0 controller from Cypress, which allows data transfers to a host computer using speeds of over 300 MB/s. The USB controller is connected to the FPGA module using a slave FIFO interface that can be configured for 16-bit or 32-bit mode using an interface clock of 100 MHz.

  • Page 33: Real-Time Clock (Rtc)

    A real-time clock is connected to the I2C bus. The RTC features a battery-buffered 128 bytes user SRAM and a temperature sensor. See Section 4 for details on the I2C bus on the Mercury KX1 FPGA module. VBAT pin of the RTC is connected to VCC_BAT on the module connector, and can be connected directly to a 3 V battery.

  • Page 34: Secure Eeprom

    ME-KX1 - R3 and newer DS28CN01 (assembly option) Maxim Table 28: EEPROM Type An example demonstrating how to read data from the EEPROM is included in the Mercury KX1 FPGA module reference design [2]. D-0000-411-002 34 / 50 Version 07, 16.02.2021...

  • Page 35: Device Configuration

    3 Device Configuration Configuration Signals Table 29 describes the most important configuration pins. Some of the pins are connected to a user I/O, as well as to a special purpose configuration pin. This is done for compatibility with other Mercury modules, on which the configuration pins can be used as user I/Os after configuration.

  • Page 36: Configuration Mode

    All configuration signals except for FPGA_MODE must be high impedance as soon as the device is released from reset. Violating this rule may damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module. Configuration Mode The FPGA_MODE signals determine whether the FPGA device is configured from the QSPI flash or serially via SPI from an external device.

  • Page 37: Pull-Up During Configuration (Pudc)

    Figure 12 illustrates the configuration of the I/O signals during power-up. Figure 13 indicates the location of the pull-up/pull-down resistors on the module PCB - upper left part on the bottom view drawing. Figure 12: Pull-Up During Configuration (PUDC) Figure 13: Pull-Up During Configuration (PUDC) Resistors - Assembly Drawing Bottom View (upper left corner) for Revision 4 Modules For details on the PUDC signal please refer to the 7 Series FPGAs Configuration User Guide [17].

  • Page 38: Jtag

    The VREF pin of the programmer must be connected to VCC_CFG_B13. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.4.3 FX3 JTAG Connector The Cypress FX3 JTAG interface are routed to the optional JTAG connector J1500.

  • Page 39: Signal Description

    3.5.1 Signal Description Signal Name Description FLASH_CLK_FPGA_CCLK Must be high impedance during configuration and operation FLASH_DO_FPGA_DIN Must be high impedance during configuration and operation FPGA_INIT# Is pulled low by the FPGA if any CRC error occurs during the configuration; it may be used as an input to delay the start of the FPGA configuration.

  • Page 40: Qspi Flash Programming Via Jtag

    Figure 14: QSPI Flash Programming from an External SPI Master - Signal Diagrams Warning! Accessing the QSPI flash directly without putting the FPGA device into reset may damage the equipped FPGA device, as well as other devices on the Mercury KX1 FPGA module. D-0000-411-002 40 / 50...

  • Page 41: Signal Description

    Table 34: Flash Programming from an External Master - Signals Description Enclustra Module Configuration Tool The QSPI flash on the Mercury KX1 FPGA module can be programmed via Cypress FX3 using the Enclustra Module Configuration Tool (MCT) [14]. Slave serial configuration is also supported by the Enclustra MCT software.

  • Page 42: I2C Communication

    4 I2C Communication Overview The I2C bus on the Mercury KX1 FPGA module is connected to the FPGA device, EEPROM, RTC and FX3 USB 3.0 controller, and is available on the module connector. This allows external devices to read the module type and to connect more devices to the I2C bus.

  • Page 43: Secure Eeprom

    An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury KX1 FPGA module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1...

  • Page 44: Product Information

    Module Product Family Reserved Revision Product Information Mercury KX1 FPGA module 0x0325 0x[XX] 0x[YY] 0x0325 [XX][YY] Table 38: Product Information Module Configuration Addr. Bits Comment Min. Value Max. Value Comment See FPGA type FPGA Type 0x08 table (Table 40) FPGA device speed grade...

  • Page 45: Fpga Device Types

    Value FPGA Device Type XC7K160T, FBG package XC7K325T, FBG package XC7K410T, FBG package XC7K160T, FFG package XC7K325T, FFG package XC7K410T, FFG package Table 40: FPGA Device Types Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses;...

  • Page 46: Operating Conditions

    5 Operating Conditions Absolute Maximum Ratings Table 41 indicates the absolute maximum ratings for Mercury KX1 FPGA module. The values given are for reference only; for details please refer to the Kintex-7 Datasheet [18]. Symbol Description Rating Unit VCC_MOD Supply voltage relative to GND -0.5 to 16...

  • Page 47: Ordering And Support

    6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-411-002 47 / 50 Version 07, 16.02.2021...
  • Page 48 ADC Parameters ..........21 MGT Switching Characteristics on the Mercury KX1 FPGA module ....22 Generated Power Supplies .
  • Page 49 EEPROM Sector 0 Memory Map ........43 Product Information .
  • Page 50 [1] Enclustra General Business Conditions http://www.enclustra.com/en/products/gbc/ [2] Mercury KX1 FPGA Module Reference Design https://github.com/enclustra [3] Mercury KX1 FPGA Module IO Net Length Excel Sheet Ask Enclustra for details [4] Mercury KX1 FPGA Module FPGA Pinout Excel Sheet Ask Enclustra for details...

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