Sharp DV-L78U Service Manual page 34

Portable dvd video player
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DV-L78U
9-10. IC602 IX0793TA
Terminal Name
Terminal
35
CLK
18
CS
34
CKE
21~24
A0~A10/AP
27~32
20
19
BS
17
RAS
16
CAS
15
WE
14, 36
DOML(U)
2, 3, 5,
I/O0~15
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
VCC/VSS
1, 25, 26
4, 7,
VCCO/VSSO
10, 13, 38, 41, 44, 47, 50
33, 37
NC
• Block Diagram
16M SDRAM
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground Isolated power supply and ground for the output buffers to provide
No Connection
Self Refresh Counter
Refresh
Refresh
Interval Timer
Counter
Address[0:10]
CLK
Precharge
Address
CKE
Register
Row Active
BS(A11)
Column Active
CS
RAS
Burst Length
CAS
Counter
WE
DOMU
DOML
Mode Register
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs
except CLK. CKE and DOML(U)
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in stanby.
Row/column address are multiplexed on the same pins.
Row address: RA0~RA10, column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during clumn address latch time.
Latches row address on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches addresses on the positive going edge of the CLK with CAS low.
Enables row access.
Enable write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when DOML(U) active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
improved noise immunity.
This pin is recommanded to be left No Connection on the device
512K x 16
Bank 0
Sense AMP & I/O gates
Column Decoder
Column Addr.
Latch & Counter
Overflow
Column Decoder
Sense AMP & I/O gates
512K x 16
Bank 1
Test Mode
34
Input Function
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O Control

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