Renesas RL78/G15 User Manual page 706

RL78/G15
Instruction Mnemonic
Group
Bit XOR1 CY, A.bit
manipulate
CY, PSW.bit
CY, saddr.bit
CY, sfr.bit
CY, [HL].bit
CY, ES:[HL].bit
SET1 A.bit
PSW.bit
!addr16.bit
ES:!addr16.bit
saddr.bit
sfr.bit
[HL].bit
ES:[HL].bit
CLR1 A.bit
PSW.bit
!addr16.bit
ES:!addr16.bit
saddr.bit
sfr.bit
[HL].bit
ES:[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Call/return CALL rp
$!addr20
!addr16
!!addr20
CALLT [addr5]
BRK —
RET —
R01UH0959EJ0110 Rev.1.10
Mar 7, 2023
Table 22-5. Operation List (11/13)
Operand Bytes
Note 1
2 1
3 1
3 1
3 1
2 1
3 2
2 1
3 4
4 2
5 3
3 2
3 2
2 2
3 3
2 1
3 4
4 2
5 3
3 2
3 2
2 2
3 3
2 1
2 1
2 1
2 3
3 3
3 3
4 3
2 5
2 5
1 6
CHAPTER 22 INSTRUCTION SET
Clock Operation
Note 2
— CY ← CY ∀ A.bit
— CY ← CY ∀ PSW.bit
— CY ← CY ∀ (saddr).bit
— CY ← CY ∀ sfr.bit
4 CY ← CY ∀ (HL).bit
5 CY ← CY ∀ (ES, HL).bit
— A.bit ← 1
— PSW.bit ← 1
— (addr16).bit ← 1
— (ES, addr16).bit ← 1
— (saddr).bit ← 1
— sfr.bit ← 1
— (HL).bit ← 1
— (ES, HL).bit ← 1
— A.bit ← 0
— PSW.bit ← 0
— (addr16).bit ← 0
— (ES, addr16).bit ← 0
— (saddr).bit ← 0
— sfr.bit ← 0
— (HL).bit ← 0
— (ES, HL).bit ← 0
— CY ← 1
— CY ← 0
¯¯
— CY ← CY
— (SP − 2) ← (PC + 2)
(SP − 4) ← (PC + 2)
SP ← SP − 4
— (SP − 2) ← (PC + 3)
(SP − 4) ← (PC + 3)
jdisp16, SP ← SP − 4
— (SP − 2) ← (PC + 3)
(SP − 4) ← (PC + 3)
SP ← SP − 4
— (SP − 2) ← (PC + 4)
(SP − 4) ← (PC + 4)
SP ← SP − 4
— (SP − 2) ← (PC + 2)
(SP − 4) ← (PC + 2)
PC ← (0000, addr5 + 1),
H
PC ← (0000, addr5),
L
SP ← SP − 4
— (SP − 1) ← PSW, (SP − 2) ← (PC + 2)
(SP − 3) ← (PC + 2)
PC ← 0000,
S
PC ← (0007FH), PC
H
SP ← SP − 4, IE ← 0
— PC ← (SP), PC ← (SP + 1),
L H
PC ← (SP + 2), SP ← SP + 4
S
Flag
Z
×
×
, (SP − 3) ← (PC + 2) ,
S H
, PC ← CS, rp,
L
, (SP − 3) ← (PC + 3) ,
S H
, PC ← PC + 3 +
L
, (SP − 3) ← (PC + 3) ,
S H
, PC ← 0000, addr16,
L
, (SP − 3) ← (PC + 4) ,
S H
, PC ← addr20,
L
, (SP − 3) ← (PC + 2) ,
S H
, PCS ← 0000,
L
,
S
, (SP − 4) ← (PC + 2) ,
H L
← (0007EH),
L
Page 706 of 765
AC CY
×
×
×
×
×
×
× ×
× ×
1
0
×