Table of Contents
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Pin
Port
No.
1
WAITODC
CPU bus control
2
NRE
CPU bus control
3
NEW
CPU bus control
4
(NC)
No Connection
5
/NFR0MCS Flash ROM chip
selection
6
NC
No Connection
7
NCS00CS
ODC chip selection
8
(NC)
No Connection
9
(NC)
No Connection
10 (NC)
No Connection
11 (NC)
No Connection
12 P57/
Low fixation
NWORD
13 A0
CPU address bus
14 A1
CPU address bus
15 A2
CPU address bus
16 A3
CPU address bus
17 3.3VDD
Connecting to power
supply.
18 (NC)
No Connection
19 VSS
GND
20 SELF TEST Drive test mode
21 (NC)
No Connection
22 3.3VDD
Connecting to power
supply.
23 CPU
Clock
CLOCK
24 (NC)
No Connection
25 MODE
Mode change
26 A4
CPU address bus
27 A5
CPU address bus
28 A6
CPU address bus
29 A7
CPU address bus
30 A8
CPU address bus
31 A9
CPU address bus
32 A10
CPU address bus
33 A11
CPU address bus
34 3.3VDD
Connecting to power
supply.
35 A12
CPU address bus
36 A13
CPU address bus
37 A14
CPU address bus
38 A15
CPU address bus
Description
I/O (V)
I
3.4
O
0
O
3.2
-
-
O
1.4
-
-
O
3.3
-
-
-
-
-
-
-
-
I
0
O
0.7
O
1.5
O
1.7
O
1.8
O
3.4
-
-
-
0
I
3.3
-
-
-
3.4
I
0
-
-
I
0
O
1.5
O
2.3
O
0.7
O
2.6
O
0.9
O
2.4
O
0.7
O
2.4
-
3.4
O
0.9
O
0.9
O
0.6
O
0.6
10
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