Table 5: Pinout Of The Phyflex-Optional Connector X2, Row A - Phytec phyFLEX-i.MX 6 Hardware Manual

phyFLEX
Pin #
X2A1
X2A2
X2A3
X2A4
X2A5
X2A6
X2A7
X2A8
X2A9
X2A10 X_SATA0_TX+
X2A11 X_SATA0_TX-
X2A12
X2A13 X_SATA0_RX+
X2A14 X_SATA0_RX-
X2A15 X_SD1_D3
X2A16 X_SD1_CMD
X2A17 X_SD1_CLK
X2A18
X2A19 reference-voltage
X2A20 X_SD1_nWP
X2A21 X_SD1_nCD
X2A22 X_SD1_D0
X2A23 X_SD1_D1
X2A24
X2A25 X_SD1_D2
X2A26 N.C.
X2A27 N.C.
X2A28 N.C.
X2A29 N.C.
X2A30
X2A31 N.C.
X2A32 N.C.
X2A33 N.C.
X2A34 N.C.
X2A35 N.C.
X2A36
X2A37 N.C.
Table 5:
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®
-i.MX 6 [PFL-A-XL1-xxx
Signal ST
X_I2C1_SDA OC-BI
X_I2C1_SCL OC-BI
reference-voltage REF_O
X_CAN0_TXD O
X_CAN0_RXD I
GND -
reference-voltage REF_O
X_HDMI0_SDA I/O
X_HDMI0_SCL I/O
LVDS_O i.MX 6 internal
LVDS_O i.MX 6 internal
GND -
LVDS_I
LVDS_I
I/O
O
O
GND -
REF_O
I
I
I/O
I/O
GND -
I/O
-
-
-
-
GND -
-
-
-
-
-
GND -
-
Pinout of the phyFLEX-optional Connector X2, Row A
Voltage Domain Description
VDD_3V3_LOGIC I2C1 data
VDD_3V3_LOGIC I2C1 clock
VDD_3V3_LOGIC I2C1 reference voltage
VDD_3V3_LOGIC CAN0 transmit
VDD_3V3_LOGIC CAN0 receive
- Ground 0 V
VDD_3V3_LOGIC CAN0 reference voltage
VDD_3V3_LOGIC HDMI0 I
VDD_3V3_LOGIC HDMI0 I
SATA0 transmit lane+
SATA0 transmit lane-
- Ground 0 V
i.MX 6 internal SATA0 receive lane+
i.MX 6 internal SATA0 receive lane-
VDD_SD1 SD1 data 3
VDD_SD1 SD1 command
VDD_SD1 SD1 clock
- Ground 0 V
VDD_SD1 SD1 reference voltage
SD1 write protection
VDD_SD1
(active low)
SD1 card detection (active
VDD_SD1
low)
VDD_SD1 SD1 data 0
VDD_SD1 SD1 data 1
- Ground 0 V
VDD_SD1 SD1 data 2
- Not connected
- Not connected
- Not connected
- Not connected
- Ground 0 V
- Not connected
- Not connected
- Not connected
- Not connected
- Not connected
- Ground 0 V
- Not connected
 PHYTEC Messtechnik GmbH 2013
2 C data
2
C clock
L-773e_2