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B.1 Test mode entering mechanism
The test mode can be activated only at IC startup. So, if test mode entry is needed, the IC needs
to be power cycled. To ensure successful enter in test mode, these steps must be followed:
1- Start with VCC=0V and VSP=0V
2- Do not apply any signal to the IC when it is switched off otherwise a biasing condition
with ESD structure may cause interference
1)
3-
Connect externally (by a relay as an example) XTAL to CLKIN to VDD.
4- Apply VCC=15V
5- Apply VSP=2.0V
6- Wait for minimum 500microseconds
7- Remove the short between CLKIN and XTAL and VDD
8- Connect 20MHz crystal oscillator (50% duty of square waveform) to CLKIN
9- Connect TST1 to the Host UART TX (transmit)
2)
10-
Connect PG pin to the Host UART RX (receive)
1)
: External 3.3V supply can be used to guarantee 100% test mode entering.
2)
: PG output needs a pull up resistor.
At this point the test mode is operative and a specific test may be chosen by programming proper
values in the proper write registers as per APPENDIX A.
To exit the test mode, simply remove the voltage applied to the IC.
CLKIN
XTAL
The block diagram of the test mode enter circuitry is shown in Fig. B-1. The timing diagram that
refers to the same circuit is shown in Fig. B-2.
As voltage is applied to the IC, the nPOReset is released and after 100 us also the nPLLReset
signal is released.
The testi signal is sampled twice, at rising edge of nPLLReset and after 1000 clock cycles of the
internal DCO (that is roughly after 100 us). If both testi samples are at 1, then the IC enters in test
mode.
When entering in the test mode the 6 Hall digital inputs become activated, hence IC consumption
may increase.
If the IC does not enter in test mode the digital pads connected to the Hall input pads are
completely disabled.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
1 us
testi
testi
Analog
filter
nPLLReset
DCO Clock
Figure B-1 Test mode entry
IRDM983-025/035MB
activate_pad
testo
testmode_enter.v
58
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