Internal Counter Register (Icr) - National Instruments GPIB-1014 User Manual

Register Descriptions

Internal Counter Register (ICR)

VMEbus Address:
AUXMR Control Code: 001 (Binary, Bits 7 - 5)
Attributes:
4 3
0 CLK3
Bit Mnemonic
4w 0
3-0w CLK[3-0]
GPIB-1014 User Manual
Base Address + 11B (hex)
Write Only, Internal to TLC
Accessed through AUXMR
2 1
CLK2 CLK1
Description
Reserved Bit
Write zero to this bit.
Clock Bits 3 through 0
The contents of the ICR are used to divide internal counters that
generate TLC state change delay times used by the IEEE 488
specification. The most familiar of these delay times, T1, is the
minimum delay between placing the data or command bytes on the
GPIB DIO lines and asserting DAV. These delay times vary
depending on the type of transfer in progress and the value of the
AUXRB bit TRI.
For proper operation, ICR should be set to eight because the TLC is
clocked at 8 MHz.
4-34
0
CLK0
W
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Chapter 4