JETWAY JNLH61S-6C Series User Manual page 25

The optional settings are: [Disabled]; [Enabled].
When set as [Enabled], the downstream port disables its traditional device number field being
0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request,
permitting access to extended functions in an ARI device immediately below the port. The default
value is disabled.
AtomicOp Requester Enable
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this function initiates AtomicOp Request only if Bus
Master Enable bit is in the command Register Set.
AtomicOp Egress Blocking
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], outbound AtomicOp Request via Egress Ports will be
blocked.
IDO Request Enable
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this permits setting the number of ID-Based Ordering
(IDO) bit (Attribute [2]) requests to be initiated.
IDO Completion Enable
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this permits setting the number of ID-Based Ordering
(IDO) bit (Attribute [2]) requests to be initiated.
LTR Mechanism Enable
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this enables the Latency Tolerance Reporting (LTR)
Mechanism.
End-End TLP Prefix Blocking
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this function will block forwarding of TLPs containing
End-End TLP Prefixes.
PCI Express GEN2 Link Register Settings:
Target Link Speed
The optional settings are: [Auto]; [Force to 2.5GT/s]; [Force to 5.0GT/s].
If supported by hardware and set to [Force to 2.5GT/s], for Downstream Ports, this sets an upper
limit on Link operational speed by restricting the values advertised by the Upstream component in
its training sequences. When [Auto] is selected HW initialized data will be used.
Clock Power Management
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], the device is permitted to use CLKREQ# signal for
power management of Link clock in accordance to protocol defined in appropriate form factor
specification.
Compliance SOS
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Enabled], this will force LTSSM to send SKP Ordered Sets
between sequences when sending Compliance Pattern or Modified Compliance Pattern.
Hardware Autonomous Width
The optional settings are: [Disabled]; [Enabled].
If supported by hardware and set to [Disabled], this will disable the hardware's ability to change link
width except width size reduction for the purpose of correction unstable link operation.
Hardware Autonomous Speed
The optional settings are: [Disabled]; [Enabled].
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