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No.
Pin Name
DAC INTERFACE
63
SCLK
64
LRCLK
73
PCM_OUT0
74
PCM_OUT1
75
PCM_OUT2
IEC958 INTERFACE (S/PDIF)
61
I958OUT
STATUS INFORMATION
PCM RELATED INFORMATION
58
SFREQ
60
DEEMPH
AUDIO VIDEO SYNCHRONIZATION
62
PTS
OTHER SIGNALS
36
CLK
43
RESET
49
TEST
52
SMODE
PIN INTERFACES
26
CLKOUT
68
VDADAC
69
VCDAC
70
VSADAC
31
VDASYS
32
VCSYS
33
VSASYS
5,11,12,24,
27,30,35,
47,50,53,
GND
55,65,71,
76,79
6,10,13,25,
28,29,34,
48,51,54,
VDD
56,66,72,
77,78
14
NC
I/O
Bit clock for the DAC
Word clock for the DAC
O
Data for the first DAC (left/right)
Data for the second DAC (centre/sub)
Data for the third DAC (leftsur/rightsur)
O
S/PDIF signal
When high, indicates that the sampling frequency is either 44.1kHz or 22.05kHz (∗).
O
When low, indicates that the sampling frequency is either 32kHz, 48kHz, 96kHz, 24kHz (∗) or 16kHz (*).
(∗) : Frequencies available for chips in software versions 4 or later only.)
O
Indicates if de-emphasis is performed
O
Indicates that a PTS has been detected, active low.
I
Master clock input signal (27MHz)
I(2)
Reset signal input, active low
I(2)
Reserved pin : to be connected to VDD
I
Reserved pin : to be connected to GND
O
System clock output
VDD Analog DAC PLL supply voltage
I
DAC PLL filter
GND Analog DAC PLL ground
VDD Analog system supply
I
System PLL filter
GND Analog system ground
GND Ground
VDD Power supply
NC
Reserved pin : to be connected GND
BD-V1100, BD-V1110
Function
61
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